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;
;	Author: MLH
;	Date: 10 Feb 2008
;	Purpose:
;		This example demonstrates the use of the EEPROM
;
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.NOLIST
.include "m32def.inc"
.LIST


.DSEG				
.ORG 0x60							; 0x60 is also the default starting address of SRAM
sram_data: .byte 100				; reserve 100 bytes of SRAM

; EEPROM segment
.ESEG
.ORG 0x0                           ; begin at first byte of EEPROM
values:                             ; starts at 0x00
    .db     1,2,3,4,0               ; initialize some EEPROM bytes with values
new_values:
	.byte	5						; reserve some bytes (no defined initial value)
text:                               
    .db     "ce-2800",0             ; initialize some bytes

; code segment for program instructions
.CSEG
.ORG 0
	rjmp start

.DEF temp=r18			            ; use arbitrary register for temporary operations

.org 0x2a
start:
; Initialize the Stack Pointer (SP) CPU register for subsequent use
	ldi	    temp, LOW(RAMEND)		; get low byte of the address of the highest byte in Data Memory we can use
	out	    SPL, temp			    ; load it into the low byte of SP
	ldi	    temp, HIGH(RAMEND)		; high byte of address of highest Data Memory byte
	out	    SPH, temp		    	; load it into the high byte of SP

;Read the numeric values from EEPROM and add them
    clr     temp
    out     EECR, temp              ; clear bits in EECR

    ldi     ZL, LOW(values)			; address of first value in EEPROM
    ldi     ZH, HIGH(values)
	ldi		XL, LOW(sram_data)		; address of first allocated byte in SRAM
	ldi		XH, HIGH(sram_data)

read:
    out     EEARL, ZL				; load the 'values' address into the EEPROM addr register
    out     EEARH, ZH

    sbi     EECR, 0                 ; read-enable EEPROM
    in      temp, EEDR				; execute the EEPROM read
	st		X+, temp				; store to SRAM
    tst     temp					; was value read 0?
    breq    read_done				; if so, we're done reading
    adiw    ZH:ZL, 1				; increment Z to point to address of next value in EEPROM
    rjmp    read					; read again


read_done:
	ldi		XL, LOW(sram_data)		; address of first byte in SRAM
	ldi		XH, HIGH(sram_data)
    ldi     ZL, LOW(new_values)		; load address of EEPROM to write to
    ldi     ZH, HIGH(new_values)
    
    clr     temp
    out     EECR, temp              ; clear bits in EECR; prepare to write
write:
    sbic    EECR, 1                 ; check if EEWE is clear (write not in progress)
    rjmp    write                   ; loop back if not clear (takes several ms)

    out     EEARL, ZL
    out     EEARH, ZH

	ld		temp, X+				; load values stored in SRAM
    out     EEDR, temp             ; load the register containing the sum to the EEPROM data register

    sbi     EECR, 2                 ; master write-enable
    sbi     EECR, 1                 ; write-enable within 4 cycles of master write enable

	tst     temp					; was value written 0?
    breq    loop_forever			; if so, we're done writing
    adiw    ZH:ZL, 1				; increment Z to point to address of next value in EEPROM
	rjmp	write
;NOTE: the SBI initiates the write, but it takes several ms to actually "burn" it in


loop_forever:                       ; sit here and spin forever
    rjmp    loop_forever