------------
-- counter_M.vhdl
--
-- 3/21/22   tj
--
-- rev 0
---
-- practice making counters
--
----------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter_M is
	generic(
				M:		positive	:= 12
	);
	port(
			i_clk:	in std_logic;
			i_rstb:	in std_logic;
			
			o_cnt1:	out std_logic_vector((M - 1) downto 0);
			o_cnt2:	out std_logic_vector((M - 1) downto 0);			
			o_cnt3:	out std_logic_vector((M - 1) downto 0)
	);
end entity;

architecture behavioral of counter_M is
	
	-- signed and unsigned signals to use in the counter
	signal cnt1_sig:	unsigned((M - 1) downto 0);
	signal cnt2_sig:	unsigned((M - 1) downto 0);
	signal cnt3_sig:	signed((M - 1) downto 0);
	
begin
	
	-- up counter
	up_cnt: process(i_clk, i_rstb)
	begin
		-- async
		if(i_rstb = '0') then
			cnt1_sig <= to_unsigned(12, M);
		-- sync
		elsif(rising_edge(i_clk)) then
			cnt1_sig <= cnt1_sig + 1;
		end if;
	end process;
	
	
	-- down counter
	dn_cnt: process(i_clk, i_rstb)
	begin
		-- async
		if(i_rstb = '0') then
			cnt2_sig <= to_unsigned(7, M);
		-- sync
		elsif(rising_edge(i_clk)) then
			cnt2_sig <= cnt2_sig - 3;
		end if;
	end process;	
	
		-- weird counter
	wd_cnt: process(i_clk, i_rstb)
	begin
		-- async
		if(i_rstb = '0') then
			cnt3_sig <= to_signed(0, M);
		-- sync
		elsif(rising_edge(i_clk)) then
			cnt3_sig <= signed(cnt2_sig) + cnt3_sig;
		end if;
	end process;
	
	-- convert back to SLV for I/O's
	o_cnt1 <= std_logic_vector(cnt1_sig);
	o_cnt2 <= std_logic_vector(cnt2_sig);
	o_cnt3 <= std_logic_vector(cnt3_sig);
	
end architecture;