------------
--   ff1_N_tb.vhdl
--
-- created 3/18/22   by tj
--
-- rev 0
----------------------
--
-- test bench for ff1_N practice building ffs
--
---------------------------
library ieee;
use ieee.std_logic_1164.all;

entity ff1_N_tb is
	generic(
				MM: positive := 21	-- plan to overwrite the default value
	);
-- no entry
end entity;

architecture testbench of ff1_N_tb is

	signal RSTB: std_logic;
	signal CLK:		std_logic;
	signal D:	std_logic_vector((MM - 1) downto 0);
	
	signal Q:	std_logic_vector((MM - 1) downto 0);
	
	constant PER: time := 20 ns;

component ff1_N is
	generic(
				N: positive := 8
	);
	port(
			i_rstb:	in	std_logic;
			i_clk:	in	std_logic;
			i_d:		in	std_logic_vector((N - 1) downto 0);
			
			o_q:		out std_logic_vector((N - 1) downto 0)
	);
end component;


begin
	dut: ff1_N
		generic map(
					N => MM		-- overwrite the default value
		)
		port map(
					i_rstb => RSTB,
					i_clk => CLK,
					i_d => D,
					o_q => Q
		);
		
	clock: process
	begin
		-- initialize
		CLK <= '0';
		
		-- start loop
		loop
			wait for PER/2;
			CLK <= not CLK;
		end loop;
	end process;
	
	reset: process
	begin
		-- initialize
		RSTB <= '0';
		
		wait for 2*PER;
		RSTB <= '1';
		
		wait;
	end process;
	
	data: process
	begin
		--initialize
		D <= (others => '0');
		
		loop
			wait for 3*PER;
			D <= not D;
		end loop;
	end process;
	
end architecture;