--------------------------------- -- -- mux_4.vhdl -- -- by: johnsontimoj -- -- created: 3/4/25 -- -- version: 0.0 -- ---------------------------------- -- -- 4 input mux -- -- inputs: a, b, c, d, sel(1:0) -- -- outputs: sel_out -- ---------------------------------- library IEEE; use ieee.std_logic_1164.all; entity mux_4 is port( i_a: in std_logic; i_b: in std_logic; i_c: in std_logic; i_d: in std_logic; i_sel: in std_logic_vector(1 downto 0); o_mux: out std_logic ); end entity; architecture behavioral of mux_4 is begin -- create the multiplexor using with-select with i_sel select o_mux <= i_a when "00", i_b when "01", i_c when "10", i_d when "11"; end architecture;