---------------------------------
--
--  mux_4.vhdl
--
--  by: johnsontimoj
--
--  created: 3/4/25
--
--  version: 0.0
--
----------------------------------
--
--  4 input mux
--
--  inputs: a, b, c, d, sel(1:0)
--
--  outputs: sel_out
--
----------------------------------
library IEEE; 
use ieee.std_logic_1164.all;

entity mux_4b is
	port(	i_data_in:		in	std_logic_vector(3 downto 0);
			i_sel:			in	std_logic_vector(1 downto 0);
			
			o_mux:			out std_logic
		 );
end entity;

architecture behavioral of mux_4b is

	
begin
	
	-- create the multiplexor using with-select
	with i_sel select o_mux <=	i_data_in(0) when "00",
										i_data_in(1) when "01",
										i_data_in(2) when "10",
										i_data_in(3) when "11";
										
end architecture;