---------------------------------
--
--  mux_4c.vhdl
--
--  by: johnsontimoj
--
--  created: 3/4/25
--
--  version: 0.0
--
----------------------------------
--
--  4 input mux using when-else
--
--  inputs: data_in 4b, sel(1:0)
--
--  outputs: sel_out
--
----------------------------------
library IEEE; 
use ieee.std_logic_1164.all;

entity mux_4c is
	port(	i_data_in:		in	std_logic_vector(3 downto 0);
			i_sel:			in	std_logic_vector(1 downto 0);
			
			o_mux:			out std_logic
		 );
end entity;

architecture behavioral of mux_4c is

	
begin
	
	-- create the multiplexor using when-else
	o_mux <=	i_data_in(0) when i_sel = "00" else
				i_data_in(1) when i_sel = "01" else
				i_data_in(2) when i_sel = "10" else
				i_data_in(3) ;
				
										
end architecture;