--------------------------------- -- -- sign_ext_4_8.vhdl -- -- by: johnsontimoj -- -- created: 3/4/25 -- -- version: 0.0 -- ---------------------------------- -- -- 4 bit to 8 bit sign extender -- -- inputs: 4 bit data -- -- outputs: 8 bit sign extended -- ---------------------------------- library IEEE; use ieee.std_logic_1164.all; entity sign_ext_4_8 is port( o_dat_in_4: in std_logic_vector(3 downto 0); o_dat_out_8: out std_logic_vector(7 downto 0) ); end entity; architecture behavioral of sign_ext_4_8 is begin -- extend the vector based on MSB o_dat_out_8 <= ("0000" & o_dat_in_4) when (o_dat_in_4(3) = '0') else ("1111" & o_dat_in_4); end architecture;