------------------------------
--
-- VGA_10x4_tb.vhdl
--
-- created: 7/15/18
-- by: johnsontimoj
-- rev: 0
--
-- testbench for VGA driver module
-- of VGA_drvr.vhdl
--
-- Uses a 10x4 configuration so you can easily see
--   the signals and transitions
--
-- brute force implementation
--
-- No PLL in simulation
-------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity VGA_10x4_tb is
		-- no port entry - testbench
end entity;

architecture testbench of VGA_10x4_tb is
	constant	Color_bits:			positive := 4;
	constant	H_counter_size:	positive := 5;
	constant	V_counter_size:	positive := 4;
	
	signal	VID_CLK		: STD_LOGIC;
	signal	RSTB			: STD_LOGIC;
	signal	H_SYNC		: STD_LOGIC;
	signal	V_SYNC		: STD_LOGIC;
	signal	PIXEL_X		: STD_LOGIC_VECTOR(h_counter_size-1 DOWNTO 0);
	signal	PIXEL_Y		: STD_LOGIC_VECTOR(v_counter_size-1 DOWNTO 0);
	signal   VID_DISPLAY	: STD_LOGIC;
	signal   RED_IN		: unsigned(color_bits-1 DOWNTO 0);
	signal	GREEN_IN		: unsigned(color_bits-1 DOWNTO 0);
	signal	BLUE_IN		: unsigned(color_bits-1 DOWNTO 0);
	signal	RED_OUT		: STD_LOGIC_VECTOR(color_bits-1 DOWNTO 0);
	signal	GREEN_OUT	: STD_LOGIC_VECTOR(color_bits-1 DOWNTO 0);
	signal	BLUE_OUT		: STD_LOGIC_VECTOR(color_bits-1 DOWNTO 0);
	
	constant	PER			:	time	:= 40 ns;

	COMPONENT VGA_drvr
		GENERIC(
			-- Default VGA 640-by-480 display parameters
			H_back_porch: 	natural:=48; 	
			H_display: 		natural:=640; 
			H_front_porch: natural:=16; 	
			H_retrace: 		natural:=96; 	
			V_back_porch: 	natural:=33; 	
			V_display: 		natural:=480; 
			V_front_porch: natural:=10; 
			V_retrace: 		natural:=2;
			Color_bits:		natural:=4;
			H_sync_polarity: std_logic:= '0';	--  depends on standard (negative -> 0), (positive -> 1)
			V_sync_polarity: std_logic:= '0';	--  depends on standard (negative -> 0), (positive -> 1)
			-- calculated based on other generic parameters
			H_counter_size: natural:= 10;		--  depends on above generic values
			V_counter_size: natural:= 10		--  depends on above generic values
		);
		PORT(
			i_vid_clk 		:	IN STD_LOGIC;
			i_rstb 			:	IN STD_LOGIC;
			o_h_sync 		: 	OUT STD_LOGIC;
			o_v_sync 		: 	OUT STD_LOGIC;
			o_pixel_x		:	OUT STD_LOGIC_VECTOR(h_counter_size-1 DOWNTO 0);
			o_pixel_y		: 	OUT STD_LOGIC_VECTOR(v_counter_size-1 DOWNTO 0);
			o_vid_display	:	OUT STD_LOGIC;
			i_red_in			:	IN STD_LOGIC_VECTOR(color_bits-1 DOWNTO 0);
			i_green_in		:	IN STD_LOGIC_VECTOR(color_bits-1 DOWNTO 0);
			i_blue_in		:	IN STD_LOGIC_VECTOR(color_bits-1 DOWNTO 0);
			o_red_out		:	OUT STD_LOGIC_VECTOR(color_bits-1 DOWNTO 0);
			o_green_out		:	OUT STD_LOGIC_VECTOR(color_bits-1 DOWNTO 0);
			o_blue_out		:	OUT STD_LOGIC_VECTOR(color_bits-1 DOWNTO 0)
		);
	END COMPONENT;

begin

	dut: VGA_drvr
		generic map(
			H_back_porch 		=> 4,--48; 	
			H_display 			=> 10,--640; 
			H_front_porch 		=> 2,--16; 	
			H_retrace 			=> 9,--96; 	
			V_back_porch 		=> 3,--33; 	
			V_display 			=> 4,--480; 
			V_front_porch 		=> 1,--10; 
			V_retrace 			=> 2,--2;
			Color_bits			=> 4,	
			H_sync_polarity 	=> '0',	--  depends on standard (negative -> 0), (positive -> 1)
			V_sync_polarity 	=> '0',	--  depends on standard (negative -> 0), (positive -> 1)
			-- calculated based on other generic parameters
			H_counter_size 	=> 5,		--  depends on above generic values
			V_counter_size 	=> 4		--  depends on above generic values
		)
		PORT MAP
		(
			i_vid_clk		=> VID_CLK,		
			i_rstb			=> RSTB	,		
			o_h_sync			=> H_SYNC,		
			o_v_sync			=> V_SYNC,		
			o_pixel_x		=> PIXEL_X,		
			o_pixel_y		=> PIXEL_Y,		
			o_vid_display	=> VID_DISPLAY,	
			i_red_in			=> std_logic_vector(RED_IN),		
			i_green_in		=> std_logic_vector(GREEN_IN),		
			i_blue_in		=> std_logic_vector(BLUE_IN),		
			o_red_out		=> RED_OUT,		
			o_green_out		=> GREEN_OUT,	
			o_blue_out		=> BLUE_OUT		
		);
		
	-------------------------------------
	-- Test processes
	-------------------------------------
	
   -- Clock process
	clock: process		-- note - no sensitivity list allowed
   begin
		VID_CLK <= '0';
		wait for PER/2;
		infinite: loop
			VID_CLK <= not VID_CLK; wait for PER/2;
		end loop;				
	end process;
	
	-- Reset process
	reset: process		-- note - no sensitivity list allowed
   begin
		RSTB <= '0'; wait for 2*PER;
		RSTB <= '1'; wait;
	end process reset;
	
	-- Run Process
	run: Process		-- note - no sensitivity list allowed
	begin
		-- Initalize values
		RED_IN <= "0101";
		GREEN_IN <= "1010";
		BLUE_IN <= "1100";
		-- wait for reset
		wait for 2*PER;
		-- run normal
		input_loop:  loop
			RED_IN <= RED_IN + 1;
			GREEN_IN <= GREEN_IN + 1;
			BLUE_IN <= BLUE_IN + 1;
			wait for PER;
		end loop;
	end process run;
	
	------------------------------------------
	-- End test processes
	------------------------------------------
	
end architecture;