/*
 * timerA_clk_input_example.c
 *
 *  Created on: 10/11/18
 *      Author: johnsontimoj
 */
//////////////////////////////////////
//
//  Timer A 2 setup to create a PWM on pin 36
//  Timer A 0 setup to to use pwm as clock
//
//  prints the signal frequency
//
////////////////////////////////////
//
//  Pin 36 is P6.6
//  P6.6 is TimerA_2, Input 3
//  Pin 48 is P7.1
//  P7.1 is TimerA_0, clk input
//
//  Use SMCLK for timer clock
//      SMCLK defaults to HSMCLK which defaults to HFXTCLK
//      all with a default of divide by 1
//          --> SMCLK = 3MHz
//
//      with no divide on the Timer A 2
//          2KHz --> 1500 counts
//          xx% duty cycle --> 1500*xx/100 counts high, 1500*(100-xx)/100 counts low
//
//      Timer A 0
//      clk is external
//
///////////////////////////////////
#include "msp.h"
#include <stdio.h>

void setup_timer_clk(void);
void setup_timer_pwm(int duty);

int main(){
    uint16_t cnt;
    int freq;

    setup_timer_pwm(40);
    setup_timer_clk();

    while(1){
        // clear timer A0
        TIMER_A0->CTL |= 0x0004;

        // delay a specified time
        __delay_cycles(15000000);

        // get result and calculate freq
        cnt = TIMER_A0->R;
        freq = cnt/5;

        // print count and frequency
        printf("Counts in 5 sec = %i,\tfrequency = %iHz\n", cnt, freq);

    } // end while

    return 0;
} // end main

void setup_timer_clk(void){
    //
    // setup pins
    //
    // P7.1 in PSEL=01 mode and set as input
    P7->SEL0 |= 0x02;
    P7->SEL1 &= ~0x02;
    P7->DIR &= ~0x02;

    //
    // TIMER_A0
    // CTL
    //        TACLK   /1   cont    noclr  no int
    // xxxx xx 00     00    10  x   0       0     x
    TIMER_A0->CTL = 0x020;

    return;
 } // end setup_timer_clk

void setup_timer_pwm(int duty){
    ///////////////////////////////////////////////////////////////////
    // duty is the percentage for duty cycle e.g. 25 --> 25% duty cycle
    ///////////////////////////////////////////////////////////////////
    //
    // setup pins
    //
    // P6.6 in PSEL=01 mode and set as output
    P6->SEL0 |= 0x40;
    P6->SEL1 &= ~0x40;
    P6->DIR |= 0x40;

    //
    // TIMER_A2
    // CTL
    //        SMCLK   /1   up    noclr  no int
    // xxxx xx 10     00   01  x   0      0     x
    TIMER_A2->CTL = 0x0210;
    //
    // CCR[0] - 1KHz
    TIMER_A2->CCR[0] = 1500;
    //
    // CCR[3]
    TIMER_A2->CCR[3] = 1500*(duty)/100;    // integer divide!!!
    //
    // CCTL[3]
    // no cap  xx  x  x  x  comp  r-s  no int  x  x  x  x
    //   00                  0    111    0
    TIMER_A2->CCTL[3] = 0x00E0;

    return;
 } // end setup_timer_pwm