/*
 * timerA_output_compare_example2.c
 *
 *  Created on: 10/9/18
 *      Author: johnsontimoj
 */
//////////////////////////////////////
//
//  Timer A setup to generate a 60% duty cycle
//  1KHz square wave on Pin 36
//
////////////////////////////////////
//
//  Pin 36 is P6.6
//  P6.6 is TimerA_2, Output 3
//
//  Use SMCLK for timer clock
//      SMCLK defaults to HSMCLK which defaults to HFXTCLK
//      all with a default of divide by 1
//          --> SMCLK = 3MHz
//      with no divide on the Timer
//          1KHz --> 3000 counts
//          60% duty cycle --> 1800 counts high, 1200 counts low
//
//  Approach 2 - don't enable on CTL, enable CCTL0 and CCTL3 -
//  then need TA2_0_IRQ and TA2_N_IRQ
//
//  Note - not concerned about the first cycle so not resetting the counter
//
///////////////////////////////////
#include "msp432.h"
#include <stdio.h>

void setup_timer(void);

int main(){
    setup_timer();

    while(1){
        ; // do nothing
    } // end while

    return 0;
} // end main


void setup_timer(void){
    //
    // setup pins
    //
    // P6.6 in PSEL=01 mode and set as output
    P6->SEL0 |= 0x40;
    P6->SEL1 &= ~0x40;
    P6->DIR |= 0x40;
    //
    // TIMER_A2
    // CTL
    //        SMCLK   /1   up    noclr  int(TAIFG)
    // xxxx xx 10     00   01  x   0     0     x
    // TIMER_A2->CTL = 0x0210;
    // approach 2
    TIMER_A2->CTL = 0x0210;
    //
    // CCR[0] - 1KHz
    TIMER_A2->CCR[0] = 3000;
    //
    // CCR[3]
    TIMER_A2->CCR[3] = 1800;
    //
    // CCTL[0]
    // no cap  xx  x  x  x  comp  xxx  int  x  out  x  x
    //   00                  0          1       0        // default output to 0
    TIMER_A2->CCTL[0] = 0x0010;
    //
    // CCTL[3]
    // no cap  xx  x  x  x  comp  xxx  int  x  out  x  x
    //   00                  0          1       0        // default output to 0
    TIMER_A2->CCTL[3] = 0x0010;
    //
    // setup NVIC
    //
    // Enable Timer A2
    // Note: Timer A2 is INTISR(12) for channel 0
    // Note: Timer A2 is INTISR(13) for channel N
    NVIC->IP[12] |= 0x40; // Set a priority
    NVIC->IP[13] |= 0x40; // Set a priority
    NVIC->ISER[0] |= 0x00003000; // ISER1 starts at 32

    return;
} // end setup_timer

//
//Interrupt routines
//
// Approach 2 - don't enable on CTL, enable CCTL0 and CCTL3 -
// then need TA2_0_IRQ and TA2_N_IRQ

void TA2_0_IRQHandler(void){
    // only get here on wrap - output 1
    TIMER_A2->CCTL[3] |= 0x0004;
    TIMER_A2->CCTL[0] &= ~0x0001; // clear flag

    return;
} // end TA2_0_IRQHandler

void TA2_N_IRQHandler(void){
    // get here on CCR(1-5) values - output 0
    // make sure some other CCR did not get you here
    if(TIMER_A2->IV == 0x06)
        TIMER_A2->CCTL[3] &= ~0x0004;

    return;
} // end TA2_N_IRQHandler