<?xml version="1.0" encoding="UTF-8"?>
<library>
 <!--  date: 2025.10.22.20:12:06 -->
 <!--  generated by: ip-make-ipx -->
 <!--   -->
 <!--     1938 in d:/nightly/25.1std/1129/w64/acds/ip/altera -->
 <!--   -->



 <component
   name="altera_avalon_new_sdram_controller"
   file="sopc_builder_ip/altera_avalon_new_sdram_controller/altera_avalon_new_sdram_controller_hw.tcl"
   displayName="SDRAM Controller Intel FPGA IP"
   version="18.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=false"
   categories="Memory Interfaces and Controllers/SDRAM"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401314928585" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <plugin
   name="altera_avalon_new_sdram_controller.qprs"
   file="sopc_builder_ip/altera_avalon_new_sdram_controller/altera_avalon_new_sdram_controller.qprs"
   displayName="altera_avalon_new_sdram_controller.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_avalon_new_sdram_controller" />
 </plugin>
 
 
 
 <plugin
   name="10GBaseR1588_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/10GBaseR1588_Native.qprs"
   displayName="10GBaseR1588_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="10GBaseR1588_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/10GBaseR1588_Native.qprs"
   displayName="10GBaseR1588_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="10GBaseR_KRFEC.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/10GBaseR_KRFEC.qprs"
   displayName="10GBaseR_KRFEC.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="10GBaseR_KRFEC.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/10GBaseR_KRFEC.qprs"
   displayName="10GBaseR_KRFEC.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="10GBaseR_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/10GBaseR_Native.qprs"
   displayName="10GBaseR_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="10GBaseR_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/10GBaseR_Native.qprs"
   displayName="10GBaseR_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="10GBaseR_ll_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/10GBaseR_ll_Native.qprs"
   displayName="10GBaseR_ll_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="10GBaseR_ll_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/10GBaseR_ll_Native.qprs"
   displayName="10GBaseR_ll_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="10g_usxgmii_ethernet.qprs"
   file="ethernet/alt_em10g32/MAC/presets/10g_usxgmii_ethernet.qprs"
   displayName="10g_usxgmii_ethernet.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="alt_em10g32" />
 </plugin>
 <plugin
   name="1g_10g_ethernet_lineside.qprs"
   file="ethernet/alt_em10g32/MAC/presets/1g_10g_ethernet_lineside.qprs"
   displayName="1g_10g_ethernet_lineside.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="alt_em10g32" />
 </plugin>
 <plugin
   name="1g_10g_ethernet_lineside_with_1588.qprs"
   file="ethernet/alt_em10g32/MAC/presets/1g_10g_ethernet_lineside_with_1588.qprs"
   displayName="1g_10g_ethernet_lineside_with_1588.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="alt_em10g32" />
 </plugin>
 <plugin
   name="1g_2_5g_10g_ethernet.qprs"
   file="ethernet/alt_em10g32/MAC/presets/1g_2_5g_10g_ethernet.qprs"
   displayName="1g_2_5g_10g_ethernet.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="alt_em10g32" />
 </plugin>
 <plugin
   name="1g_2_5g_ethernet.qprs"
   file="ethernet/alt_em10g32/MAC/presets/1g_2_5g_ethernet.qprs"
   displayName="1g_2_5g_ethernet.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="alt_em10g32" />
 </plugin>
 <plugin
   name="1g_2_5g_with_1588_ethernet.qprs"
   file="ethernet/alt_em10g32/MAC/presets/1g_2_5g_with_1588_ethernet.qprs"
   displayName="1g_2_5g_with_1588_ethernet.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="alt_em10g32" />
 </plugin>
 <plugin
   name="3G-SDI-UK.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SDI/3G-SDI-UK.qprs"
   displayName="3G-SDI-UK.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="3G-SDI-UK.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/3G-SDI-UK.qprs"
   displayName="3G-SDI-UK.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="3G-SDI-US.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SDI/3G-SDI-US.qprs"
   displayName="3G-SDI-US.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="3G-SDI-US.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/3G-SDI-US.qprs"
   displayName="3G-SDI-US.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="ASI_1.35Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/ASI_1.35Gbps.qprs"
   displayName="ASI_1.35Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="ASI_1.35Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/ASI_1.35Gbps.qprs"
   displayName="ASI_1.35Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <component
   name="AVMM"
   file="altera_hmcc/a10_example_design/src/AVMM.qsys"
   displayName="AVMM"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="AVMM"
   file="altera_hmcc_mtaps/a10_example_design/src/AVMM.qsys"
   displayName="AVMM"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="AVMM"
   file="altera_hmcc_mtaps/s10_example_design/src/AVMM.qsys"
   displayName="AVMM"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="Advanced_Clocking_Mode_2x10G.qprs"
   file="seriallite_iii/src/presets/Advanced_Clocking_Mode_2x10G.qprs"
   displayName="Advanced_Clocking_Mode_2x10G.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="seriallite_iii_a10" />
 </plugin>
 <plugin
   name="Advanced_Clocking_Mode_2x10G_StratixV.qprs"
   file="seriallite_iii/src/presets/Advanced_Clocking_Mode_2x10G_StratixV.qprs"
   displayName="Advanced_Clocking_Mode_2x10G_StratixV.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="seriallite_iii_sv" />
 </plugin>
 <plugin
   name="Advanced_Clocking_Mode_6x12.5G.qprs"
   file="altera_sl3/ed/presets/Advanced_Clocking_Mode_6x12.5G.qprs"
   displayName="Advanced_Clocking_Mode_6x12.5G.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_sl3" />
 </plugin>
 <plugin
   name="Advanced_Clocking_Mode_6x12.5G.qprs"
   file="seriallite_iii/src/presets/Advanced_Clocking_Mode_6x12.5G.qprs"
   displayName="Advanced_Clocking_Mode_6x12.5G.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="seriallite_iii_a10" />
 </plugin>
 <component
   name="Altera_UP_Flash_Memory_IP_Core_Avalon_Interface"
   file="university_program/memory/altera_up_flash_memory/Altera_UP_Flash_Memory_IP_Core_Avalon_Interface_hw.tcl"
   displayName="Intel FPGA University Program Flash Memory IP"
   version="18.0"
   description="Flash Memory Interface Module"
   tags="CONNECTION_TYPES=avalon,clock,conduit,reset"
   categories="University Program/Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/memory/altera_up_flash_memory/doc/Flash_Memory_IP_Core.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file://ip/altera/university_program/memory/altera_up_flash_memory/doc/Flash_Memory_IP_Core.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="Altera_UP_SD_Card_Avalon_Interface"
   file="university_program/memory/altera_up_sd_card_avalon_interface/Altera_UP_SD_Card_Avalon_Interface_hw.tcl"
   displayName="SD Card Interface"
   version="18.0"
   description="A module that allows communication with an SD Card"
   tags="CONNECTION_TYPES=avalon,clock,conduit,reset"
   categories="University Program/Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/memory/altera_up_sd_card_avalon_interface/doc/SD_Card_Interface_for_SoPC_Builder.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/memory/altera_up_sd_card_avalon_interface/doc/SD_Card_Interface_for_SoPC_Builder.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <plugin
   name="Altera_UP_SD_Card_Avalon_Interface_driver"
   file="university_program/memory/altera_up_sd_card_avalon_interface/Altera_UP_SD_Card_Avalon_Interface_sw.tcl"
   displayName="Altera_UP_SD_Card_Avalon_Interface_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=Altera_UP_SD_Card_Avalon_Interface"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="Avalon_Audio_and_Video_driver"
   file="university_program/audio_video/altera_up_avalon_audio_and_video_config/altera_up_avalon_audio_and_video_config_sw.tcl"
   displayName="Avalon_Audio_and_Video_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_audio_and_video_config"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="Avalon_Audio_driver"
   file="university_program/audio_video/altera_up_avalon_audio/altera_up_avalon_audio_sw.tcl"
   displayName="Avalon_Audio_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_audio"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="BackPlane_wo_1588.qprs"
   file="alt_xcvr/altera_xcvr_10gbase_kr/altera_xcvr_10gbase_kr/presets/BackPlane_wo_1588.qprs"
   displayName="BackPlane_wo_1588.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_10gbase_kr" />
 </plugin>
 <plugin
   name="BackPlane_wo_1588.qprs"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/altera_xcvr_10gkr_a10/presets/BackPlane_wo_1588.qprs"
   displayName="BackPlane_wo_1588.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_10gkr_a10" />
 </plugin>
 <plugin
   name="CEI-6G.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/CEI-6G.qprs"
   displayName="CEI-6G.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="CEI-6G.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/CEI-6G.qprs"
   displayName="CEI-6G.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="CPRI-614.4Mbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/av/presets/CPRI-614.4Mbps.qprs"
   displayName="CPRI-614.4Mbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_av" />
 </plugin>
 <plugin
   name="CPRI-614.4Mbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/CPRI-614.4Mbps.qprs"
   displayName="CPRI-614.4Mbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="CPRI-614.4Mbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/cv/presets/CPRI-614.4Mbps.qprs"
   displayName="CPRI-614.4Mbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_cv" />
 </plugin>
 <plugin
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 <plugin
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   file="ethernet/alt_em10g32/MAC/presets/Ethernet_10GBaseR_register_mode.qprs"
   displayName="Ethernet_10GBaseR_register_mode.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="alt_em10g32" />
 </plugin>
 <plugin
   name="GIGE-1.25Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/av/presets/GIGE-1.25Gbps.qprs"
   displayName="GIGE-1.25Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_av" />
 </plugin>
 <plugin
   name="GIGE-1.25Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/GIGE-1.25Gbps.qprs"
   displayName="GIGE-1.25Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="GIGE-1.25Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/cv/presets/GIGE-1.25Gbps.qprs"
   displayName="GIGE-1.25Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_cv" />
 </plugin>
 <plugin
   name="GIGE-1.25Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/GIGE-1.25Gbps.qprs"
   displayName="GIGE-1.25Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="GIGE-2.5Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/av/presets/GIGE-2.5Gbps.qprs"
   displayName="GIGE-2.5Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_av" />
 </plugin>
 <plugin
   name="GIGE-2.5Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/GIGE-2.5Gbps.qprs"
   displayName="GIGE-2.5Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="GIGE-2.5Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/cv/presets/GIGE-2.5Gbps.qprs"
   displayName="GIGE-2.5Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_cv" />
 </plugin>
 <plugin
   name="GIGE-2.5Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/GIGE-2.5Gbps.qprs"
   displayName="GIGE-2.5Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="GIGE_1G25_1588_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/GIGE_1G25_1588_Native.qprs"
   displayName="GIGE_1G25_1588_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="GIGE_1G25_1588_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/GIGE_1G25_1588_Native.qprs"
   displayName="GIGE_1G25_1588_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="GIGE_1G25_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/GIGE_1G25_Native.qprs"
   displayName="GIGE_1G25_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="GIGE_1G25_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/GIGE_1G25_Native.qprs"
   displayName="GIGE_1G25_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="GT_12890M625_x1_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_s10/preset/GT_12890M625_x1_atx.qprs"
   displayName="GT_12890M625_x1_atx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_s10" />
 </plugin>
 <plugin
   name="GT_12890M625_x1_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_vi/preset/GT_12890M625_x1_atx.qprs"
   displayName="GT_12890M625_x1_atx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_a10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_Bonded_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_s10/preset/GX_1250Mhz_Bonded_atx.qprs"
   displayName="GX_1250Mhz_Bonded_atx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_s10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_Bonded_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_vi/preset/GX_1250Mhz_Bonded_atx.qprs"
   displayName="GX_1250Mhz_Bonded_atx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_a10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_Bonded_fpll.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_fpll_vi/preset/GX_1250Mhz_Bonded_fpll.qprs"
   displayName="GX_1250Mhz_Bonded_fpll.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_fpll_a10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_x1_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_s10/preset/GX_1250Mhz_x1_atx.qprs"
   displayName="GX_1250Mhz_x1_atx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_s10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_x1_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_vi/preset/GX_1250Mhz_x1_atx.qprs"
   displayName="GX_1250Mhz_x1_atx.qprs"
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   description=""
   tags=""
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   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_a10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_x1_cmu.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_cdr_pll_s10/preset/GX_1250Mhz_x1_cmu.qprs"
   displayName="GX_1250Mhz_x1_cmu.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_cdr_pll_s10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_x1_cmu.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_cdr_pll_vi/preset/GX_1250Mhz_x1_cmu.qprs"
   displayName="GX_1250Mhz_x1_cmu.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_cdr_pll_a10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_x1_fpll.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_fpll_vi/preset/GX_1250Mhz_x1_fpll.qprs"
   displayName="GX_1250Mhz_x1_fpll.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_fpll_a10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_xn_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_s10/preset/GX_1250Mhz_xn_atx.qprs"
   displayName="GX_1250Mhz_xn_atx.qprs"
   version="0.0"
   description=""
   tags=""
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   type="com.altera.sopcmodel.util.IElementPresetList"
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_s10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_xn_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_vi/preset/GX_1250Mhz_xn_atx.qprs"
   displayName="GX_1250Mhz_xn_atx.qprs"
   version="0.0"
   description=""
   tags=""
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   type="com.altera.sopcmodel.util.IElementPresetList"
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_a10" />
 </plugin>
 <plugin
   name="GX_1250Mhz_xn_fpll.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_fpll_vi/preset/GX_1250Mhz_xn_fpll.qprs"
   displayName="GX_1250Mhz_xn_fpll.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_fpll_a10" />
 </plugin>
 <plugin
   name="HD-SDI-UK.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SDI/HD-SDI-UK.qprs"
   displayName="HD-SDI-UK.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="HD-SDI-UK.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/HD-SDI-UK.qprs"
   displayName="HD-SDI-UK.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="HD-SDI-US.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SDI/HD-SDI-US.qprs"
   displayName="HD-SDI-US.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="HD-SDI-US.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/HD-SDI-US.qprs"
   displayName="HD-SDI-US.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="HDMI_1_4_RX_2_SYMBOLS_PER_CLOCK.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/av/presets/HDMI_1_4_RX_2_SYMBOLS_PER_CLOCK.qprs"
   displayName="HDMI_1_4_RX_2_SYMBOLS_PER_CLOCK.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_av" />
 </plugin>
 <plugin
   name="HDMI_1_4_RX_2_SYMBOLS_PER_CLOCK.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/HDMI_1_4_RX_2_SYMBOLS_PER_CLOCK.qprs"
   displayName="HDMI_1_4_RX_2_SYMBOLS_PER_CLOCK.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="HDMI_1_4_TX_2_SYMBOLS_PER_CLOCK.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/av/presets/HDMI_1_4_TX_2_SYMBOLS_PER_CLOCK.qprs"
   displayName="HDMI_1_4_TX_2_SYMBOLS_PER_CLOCK.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_av" />
 </plugin>
 <plugin
   name="HDMI_1_4_TX_2_SYMBOLS_PER_CLOCK.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/HDMI_1_4_TX_2_SYMBOLS_PER_CLOCK.qprs"
   displayName="HDMI_1_4_TX_2_SYMBOLS_PER_CLOCK.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="HDMI_2_0_RX_4_SYMBOLS_PER_CLOCK.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/av/presets/HDMI_2_0_RX_4_SYMBOLS_PER_CLOCK.qprs"
   displayName="HDMI_2_0_RX_4_SYMBOLS_PER_CLOCK.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_av" />
 </plugin>
 <plugin
   name="HDMI_2_0_TX_4_SYMBOLS_PER_CLOCK.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/av/presets/HDMI_2_0_TX_4_SYMBOLS_PER_CLOCK.qprs"
   displayName="HDMI_2_0_TX_4_SYMBOLS_PER_CLOCK.qprs"
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   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_av" />
 </plugin>
 <component
   name="IOPLL_half_clk_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER_RegMode/rtl/IOPLL_half_clk/IOPLL_half_clk_a10.qsys"
   displayName="IOPLL_half_clk_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="Interlaken.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/Interlaken.qprs"
   displayName="Interlaken.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="Interlaken_10x12G5_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/Interlaken_10x12G5_Native.qprs"
   displayName="Interlaken_10x12G5_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="Interlaken_10x12G5_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/Interlaken_10x12G5_Native.qprs"
   displayName="Interlaken_10x12G5_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="Interlaken_1x6G25_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/Interlaken_1x6G25_Native.qprs"
   displayName="Interlaken_1x6G25_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="Interlaken_1x6G25_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/Interlaken_1x6G25_Native.qprs"
   displayName="Interlaken_1x6G25_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="Interlaken_6x10G3_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/Interlaken_6x10G3_Native.qprs"
   displayName="Interlaken_6x10G3_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
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 <plugin
   name="PIPE_Gen3x1_100Mhz_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_s10/preset/PIPE_Gen3x1_100Mhz_atx.qprs"
   displayName="PIPE_Gen3x1_100Mhz_atx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_s10" />
 </plugin>
 <plugin
   name="PIPE_Gen3x1_100Mhz_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_vi/preset/PIPE_Gen3x1_100Mhz_atx.qprs"
   displayName="PIPE_Gen3x1_100Mhz_atx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_a10" />
 </plugin>
 <plugin
   name="PIPE_Gen3x8_100Mhz_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_s10/preset/PIPE_Gen3x8_100Mhz_atx.qprs"
   displayName="PIPE_Gen3x8_100Mhz_atx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_s10" />
 </plugin>
 <plugin
   name="PIPE_Gen3x8_100Mhz_atx.qprs"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_atx_pll_vi/preset/PIPE_Gen3x8_100Mhz_atx.qprs"
   displayName="PIPE_Gen3x8_100Mhz_atx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_atx_pll_a10" />
 </plugin>
 <plugin
   name="Quad_Speed_ethernet_lineside.qprs"
   file="ethernet/alt_em10g32/MAC/presets/Quad_Speed_ethernet_lineside.qprs"
   displayName="Quad_Speed_ethernet_lineside.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="alt_em10g32" />
 </plugin>
 <plugin
   name="Quad_Speed_ethernet_lineside_with_1588.qprs"
   file="ethernet/alt_em10g32/MAC/presets/Quad_Speed_ethernet_lineside_with_1588.qprs"
   displayName="Quad_Speed_ethernet_lineside_with_1588.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="alt_em10g32" />
 </plugin>
 <plugin
   name="RTL_State_Machine_Control_Example_Design.qprs"
   file="altera_jesd204/src/top/RTL_State_Machine_Control_Example_Design.qprs"
   displayName="RTL_State_Machine_Control_Example_Design.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_jesd204" />
 </plugin>
 <plugin
   name="S25FL127S.qprs"
   file="pgm/altera_asmi_parallel2/presets/S25FL127S.qprs"
   displayName="S25FL127S.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_asmi_parallel2" />
 </plugin>
 <plugin
   name="SAS-Gen1.1.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SAS/SAS-Gen1.1.qprs"
   displayName="SAS-Gen1.1.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="SAS-Gen1.1.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/SAS-Gen1.1.qprs"
   displayName="SAS-Gen1.1.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="SAS-Gen1.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SAS/SAS-Gen1.qprs"
   displayName="SAS-Gen1.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="SAS-Gen1.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/SAS-Gen1.qprs"
   displayName="SAS-Gen1.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="SAS-Gen2.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SAS/SAS-Gen2.qprs"
   displayName="SAS-Gen2.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="SAS-Gen2.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/SAS-Gen2.qprs"
   displayName="SAS-Gen2.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="SAS_Gen1_1_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SAS_Gen1_1_Native.qprs"
   displayName="SAS_Gen1_1_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="SAS_Gen1_1_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SAS_Gen1_1_Native.qprs"
   displayName="SAS_Gen1_1_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SAS_Gen1_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SAS_Gen1_Native.qprs"
   displayName="SAS_Gen1_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="SAS_Gen1_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SAS_Gen1_Native.qprs"
   displayName="SAS_Gen1_Native.qprs"
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   tags=""
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   type="com.altera.sopcmodel.util.IElementPresetList"
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SAS_Gen2_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SAS_Gen2_Native.qprs"
   displayName="SAS_Gen2_Native.qprs"
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   tags=""
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  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="SAS_Gen2_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SAS_Gen2_Native.qprs"
   displayName="SAS_Gen2_Native.qprs"
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   tags=""
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  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SATA-Gen1.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SATA/SATA-Gen1.qprs"
   displayName="SATA-Gen1.qprs"
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   tags=""
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  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="SATA-Gen1.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/SATA-Gen1.qprs"
   displayName="SATA-Gen1.qprs"
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   tags=""
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="SATA-Gen2.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SATA/SATA-Gen2.qprs"
   displayName="SATA-Gen2.qprs"
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   tags=""
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  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="SATA-Gen2.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/SATA-Gen2.qprs"
   displayName="SATA-Gen2.qprs"
   version="0.0"
   description=""
   tags=""
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="SATA-Gen3.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SATA/SATA-Gen3.qprs"
   displayName="SATA-Gen3.qprs"
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   tags=""
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   type="com.altera.sopcmodel.util.IElementPresetList"
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  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="SATA-Gen3.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/SATA-Gen3.qprs"
   displayName="SATA-Gen3.qprs"
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  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="SATA_Gen1_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SATA_Gen1_Native.qprs"
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  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
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   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SATA_Gen1_Native.qprs"
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 </plugin>
 <plugin
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   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SATA_Gen2_Native.qprs"
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 </plugin>
 <plugin
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   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SATA_Gen2_Native.qprs"
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 </plugin>
 <plugin
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   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SATA_Gen3_Native.qprs"
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   tags=""
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 </plugin>
 <plugin
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  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
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   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SONET/SDH_OC-12.qprs"
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  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
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   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/SDH_OC-12.qprs"
   displayName="SDH_OC-12.qprs"
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  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
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   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SONET/SDH_OC-48.qprs"
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 </plugin>
 <plugin
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   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/SDH_OC-48.qprs"
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 <plugin
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 <plugin
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 </plugin>
 <plugin
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 </plugin>
 <plugin
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 </plugin>
 <plugin
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 <plugin
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 <plugin
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 <plugin
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 <plugin
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 </plugin>
 <plugin
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 </plugin>
 <plugin
   name="SDI_Multi_rate_up_to_12G_Rx.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SDI_Multi_rate_up_to_12G_Rx.qprs"
   displayName="SDI_Multi_rate_up_to_12G_Rx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SDI_Multi_rate_up_to_12G_Tx.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SDI_Multi_rate_up_to_12G_Tx.qprs"
   displayName="SDI_Multi_rate_up_to_12G_Tx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SDI_Triple_rate_Rx.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SDI_Triple_rate_Rx.qprs"
   displayName="SDI_Triple_rate_Rx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="SDI_Triple_rate_Rx.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SDI_Triple_rate_Rx.qprs"
   displayName="SDI_Triple_rate_Rx.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SFIS_4x11G3_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SFIS_4x11G3_Native.qprs"
   displayName="SFIS_4x11G3_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="SFIS_4x11G3_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SFIS_4x11G3_Native.qprs"
   displayName="SFIS_4x11G3_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SONET_SDH_OC_12.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SONET_SDH_OC_12.qprs"
   displayName="SONET_SDH_OC_12.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="SONET_SDH_OC_12.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SONET_SDH_OC_12.qprs"
   displayName="SONET_SDH_OC_12.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SONET_SDH_OC_48.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SONET_SDH_OC_48.qprs"
   displayName="SONET_SDH_OC_48.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="SONET_SDH_OC_48.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SONET_SDH_OC_48.qprs"
   displayName="SONET_SDH_OC_48.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SONET_SDH_OC_96.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SONET_SDH_OC_96.qprs"
   displayName="SONET_SDH_OC_96.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="SONET_SDH_OC_96.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SONET_SDH_OC_96.qprs"
   displayName="SONET_SDH_OC_96.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SRIO_1G25_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_s10/presets/SRIO_1G25_Native.qprs"
   displayName="SRIO_1G25_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_s10" />
 </plugin>
 <plugin
   name="SRIO_1G25_Native.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/presets/SRIO_1G25_Native.qprs"
   displayName="SRIO_1G25_Native.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_a10" />
 </plugin>
 <plugin
   name="SerialRapidIO_1.25Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/presets/SerialRapidIO_1.25Gbps.qprs"
   displayName="SerialRapidIO_1.25Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_avgz" />
 </plugin>
 <plugin
   name="SerialRapidIO_1.25Gbps.qprs"
   file="alt_xcvr/altera_xcvr_native_phy/sv/presets/SerialRapidIO_1.25Gbps.qprs"
   displayName="SerialRapidIO_1.25Gbps.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_native_sv" />
 </plugin>
 <plugin
   name="Standard_Clocking_Mode_2x10G.qprs"
   file="seriallite_iii/src/presets/Standard_Clocking_Mode_2x10G.qprs"
   displayName="Standard_Clocking_Mode_2x10G.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="seriallite_iii_a10" />
 </plugin>
 <plugin
   name="Standard_Clocking_Mode_2x10G_StratixV.qprs"
   file="seriallite_iii/src/presets/Standard_Clocking_Mode_2x10G_StratixV.qprs"
   displayName="Standard_Clocking_Mode_2x10G_StratixV.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="seriallite_iii_sv" />
 </plugin>
 <plugin
   name="Standard_Clocking_Mode_6x12.5G.qprs"
   file="altera_sl3/ed/presets/Standard_Clocking_Mode_6x12.5G.qprs"
   displayName="Standard_Clocking_Mode_6x12.5G.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_sl3" />
 </plugin>
 <plugin
   name="Standard_Clocking_Mode_6x12.5G.qprs"
   file="seriallite_iii/src/presets/Standard_Clocking_Mode_6x12.5G.qprs"
   displayName="Standard_Clocking_Mode_6x12.5G.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="seriallite_iii_a10" />
 </plugin>
 <component
   name="address_decode_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER/rtl/address_decoder/address_decode_a10.qsys"
   displayName="address_decode_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decode_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER_RegMode/rtl/address_decoder/address_decode_a10.qsys"
   displayName="address_decode_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10G_USXGMII/rtl/address_decoder/address_decoder_channel_a10.qsys"
   displayName="address_decoder_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE/rtl/address_decoder/address_decoder_channel_a10.qsys"
   displayName="address_decoder_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/address_decoder/address_decoder_channel_a10.qsys"
   displayName="address_decoder_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE/rtl/address_decoder/address_decoder_channel_a10.qsys"
   displayName="address_decoder_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/address_decoder/address_decoder_channel_a10.qsys"
   displayName="address_decoder_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_multi_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10G_USXGMII/rtl/address_decoder/address_decoder_multi_channel_a10.qsys"
   displayName="address_decoder_multi_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_multi_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE/rtl/address_decoder/address_decoder_multi_channel_a10.qsys"
   displayName="address_decoder_multi_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_multi_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/address_decoder/address_decoder_multi_channel_a10.qsys"
   displayName="address_decoder_multi_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_multi_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE/rtl/address_decoder/address_decoder_multi_channel_a10.qsys"
   displayName="address_decoder_multi_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_multi_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/address_decoder/address_decoder_multi_channel_a10.qsys"
   displayName="address_decoder_multi_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_top_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10G_USXGMII/rtl/address_decoder/address_decoder_top_a10.qsys"
   displayName="address_decoder_top_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_top_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE/rtl/address_decoder/address_decoder_top_a10.qsys"
   displayName="address_decoder_top_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_top_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/address_decoder/address_decoder_top_a10.qsys"
   displayName="address_decoder_top_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_top_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE/rtl/address_decoder/address_decoder_top_a10.qsys"
   displayName="address_decoder_top_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="address_decoder_top_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/address_decoder/address_decoder_top_a10.qsys"
   displayName="address_decoder_top_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="ahb"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="ahb"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="ahb_master"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="AHB Master"
   version="25.1"
   description="AHB master interfaces are used to issue read and write commands to slave interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="ahb_slave"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="AHB Slave"
   version="25.1"
   description="AHB slave interfaces are used to accept and respond to read and write commands issued by master interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <component
   name="alt_aeuex_jtag_avalon"
   file="ethernet/alt_e2550/example_project/common/alt_aeuex_jtag_avalon.qsys"
   displayName="alt_aeuex_jtag_avalon"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_e100_jtag_avalon"
   file="alt_eth_40g_100g/100gbe/example/common/alt_e100_jtag_avalon.qsys"
   displayName="alt_e100_jtag_avalon"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_e25"
   file="ethernet/alt_e2550/hwtcl/alt_e25_hw.tcl"
   displayName="25G Ethernet Arria 10 IP"
   version="25.1"
   description="25G"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Ethernet"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="::alt_e2550::module::elaborate" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::alt_e2550::module::upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="::alt_e2550::parameters::validate" />
  <documentUrl displayName="DATASHEET" type="DATASHEET" url="" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/ewo1447742896786.html#ewo1450736893437" />
 </component>
 <component
   name="alt_e2550"
   file="ethernet/alt_e2550/hwtcl/alt_e2550_hw.tcl"
   displayName="25G/50G Ethernet IP"
   version="25.1"
   description="25G/50G"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="false" />
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   version="25.1"
   description="Convert incomplete AXI4 interface to complete AXI4 interface"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="alt_hiconnect_burst_adapter"
   file="iconnect/alt_hiconnect_burst_adapter/alt_hiconnect_burst_adapter_hw.tcl"
   displayName="Memory Mapped Burst Adapter"
   version="25.1"
   description="Accommodates the burst capabilities of each interface in the system, including interfaces that do not support burst transfers, translating burst sizes as required."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_dc_fifo"
   file="iconnect/alt_hiconnect_dc_fifo/alt_hiconnect_dc_fifo_hw.tcl"
   displayName="Avalon-ST Dual Clock FIFO"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/nios2/qts_qii55014.pdf" />
 </component>
 <component
   name="alt_hiconnect_demux"
   file="iconnect/alt_hiconnect_demux/alt_hiconnect_demux_hw.tcl"
   displayName="Demultiplexer"
   version="16.0"
   description="Demux with one-hot select signals"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_demux2"
   file="iconnect/alt_hiconnect_demux2/alt_hiconnect_demux_hw.tcl"
   displayName="Demultiplexer"
   version="25.1"
   description="Demux with one-hot select signals"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_handshake_clock_crosser"
   file="iconnect/alt_hiconnect_handshake_clock_crosser/alt_hiconnect_handshake_clock_crosser_hw.tcl"
   displayName="Avalon-ST Handshake Clock Crosser"
   version="25.1"
   description="Connects streams that operate at different frequencie using a hand-shaking protocol to propagate transfer control signals and responses across the clock boundary and responses in the other direction."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_mux"
   file="iconnect/alt_hiconnect_mux/alt_hiconnect_mux_hw.tcl"
   displayName="Multiplexer"
   version="25.1"
   description="Mux with one-hot select signals"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_mux2"
   file="iconnect/alt_hiconnect_mux2/alt_hiconnect_mux_hw.tcl"
   displayName="Multiplexer"
   version="25.1"
   description="Mux with one-hot select signals"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_router"
   file="iconnect/alt_hiconnect_router/alt_hiconnect_router_hw.tcl"
   displayName="Memory Mapped Router"
   version="25.1"
   description="Routes command packets from the master to the slave and response packets from the slave to the master."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_router2"
   file="iconnect/alt_hiconnect_router2/alt_hiconnect_router_hw.tcl"
   displayName="Memory Mapped Router"
   version="25.1"
   description="Routes command packets from the master to the slave and response packets from the slave to the master."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_sc_fifo"
   file="iconnect/alt_hiconnect_sc_fifo/alt_hiconnect_sc_fifo_hw.tcl"
   displayName="Avalon-ST Single Clock FIFO"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/nios2/qts_qii55014.pdf" />
 </component>
 <component
   name="alt_hiconnect_scheduler"
   file="iconnect/alt_hiconnect_scheduler/alt_hiconnect_scheduler_hw.tcl"
   displayName="Scheduler"
   version="1.2"
   description=""
   tags="AUTHORSHIP= /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="alt_hiconnect_skid_buffer"
   file="iconnect/alt_hiconnect_skid_buffer/alt_hiconnect_skid_buffer_hw.tcl"
   displayName="Avalon-ST Skid Buffer"
   version="25.1"
   description="Inserts a single pipeline (register) stage in the Avalon-ST command and response datapaths. Receives data on its Avalon-ST sink interfaces and drives it unchanged on its Avalon-ST source interface."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_squish"
   file="iconnect/alt_hiconnect_squish/alt_hiconnect_squish_hw.tcl"
   displayName="Avalon-ST Squish"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_st_reg"
   file="iconnect/alt_hiconnect_st_reg/alt_hiconnect_st_reg_hw.tcl"
   displayName="Avalon-ST Register"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_traffic_limiter"
   file="iconnect/alt_hiconnect_traffic_limiter/alt_hiconnect_traffic_limiter_hw.tcl"
   displayName="Memory Mapped Traffic Limiter"
   version="25.1"
   description="Ensures the responses arrive in order, simplifying the Qsys response network."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_unsquish"
   file="iconnect/alt_hiconnect_unsquish/alt_hiconnect_unsquish_hw.tcl"
   displayName="Avalon-ST Unsquish"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_hiconnect_width_adapter"
   file="iconnect/alt_hiconnect_width_adapter/alt_hiconnect_width_adapter_hw.tcl"
   displayName="Memory Mapped Width Adapter"
   version="25.1"
   description="Converts between Avalon-MM master and slaves with different data and byte enable widths."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped Alpha"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="alt_interlaken_12lane_10g"
   file="alt_interlaken/design_examples/alt_interlaken_12lane_10g/alt_interlaken_12lane_10g.qsys"
   displayName="alt_interlaken_12lane_10g"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_interlaken_20lane_6g"
   file="alt_interlaken/design_examples/alt_interlaken_20lane_6g/alt_interlaken_20lane_6g.qsys"
   displayName="alt_interlaken_20lane_6g"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_interlaken_4lane_3g"
   file="alt_interlaken/design_examples/alt_interlaken_4lane_3g/alt_interlaken_4lane_3g.qsys"
   displayName="alt_interlaken_4lane_3g"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_interlaken_8lane_6g"
   file="alt_interlaken/design_examples/alt_interlaken_8lane_6g/alt_interlaken_8lane_6g.qsys"
   displayName="alt_interlaken_8lane_6g"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_interlaken_pcs_siv"
   file="alt_interlaken/alt_interlaken_pcs_siv/alt_interlaken_pcs_siv_hw.tcl"
   displayName="ALT_Interlaken_PCS_SIV"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Interfaces|Interlaken"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="alt_interlaken_pcs_siv_compose" />
  <tag2 key="ELABORATION_CALLBACK" value="alt_interlaken_pcs_siv_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="alt_jtag_csr_master_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10G_USXGMII/rtl/jtag_avalon_master/alt_jtag_csr_master_a10.qsys"
   displayName="alt_jtag_csr_master_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_jtag_csr_master_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G/rtl/jtag_avalon_master/alt_jtag_csr_master_a10.qsys"
   displayName="alt_jtag_csr_master_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_jtag_csr_master_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_10G/rtl/jtag_avalon_master/alt_jtag_csr_master_a10.qsys"
   displayName="alt_jtag_csr_master_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_jtag_csr_master_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_1588v2/rtl/jtag_avalon_master/alt_jtag_csr_master_a10.qsys"
   displayName="alt_jtag_csr_master_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_jtagavalon_wrapper"
   file="sld/mm/alt_jtagavalon_wrapper/alt_jtagavalon_hw.tcl"
   displayName="JTAG Avalon"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=avalon,clock /// INTERNAL_COMPONENT=true"
   categories="Bridges and Adapters/Streaming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="alt_mem_ddrx_mm_st_converter"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr_controller_110/rtl/alt_mem_ddrx_mm_st_converter/alt_mem_ddrx_mm_st_converter_hw.tcl"
   displayName="Altera Nextgen Memory Controller MM-ST Adapter"
   version="25.1"
   description="Altera Nextgen Memory Controller MM-ST Adapter"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controller Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="alt_mem_if_civ_ddr2_controller"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_civ_ddr2_controller/alt_mem_if_civ_ddr2_controller_hw.tcl"
   displayName="DDR2 SDRAM Controller for Cyclone IV alt_mem_if (High Performance Controller II)"
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   description="DDR2 SDRAM Controller for Cyclone IV alt_mem_if (High Performance Controller II)"
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   categories="Memory Interfaces and Controllers/Memory Interfaces with AltMemPHY"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV GX /// Cyclone IV E" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2
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 </component>
 <component
   name="alt_mem_if_civ_ddr2_emif"
   file="alt_mem_if/alt_mem_if_interfaces/alt_mem_if_civ_ddr2_emif/alt_mem_if_civ_ddr2_emif_hw.tcl"
   displayName="DDR2 SDRAM Controller with AltMemPHY IP"
   version="1.0.0"
   description="DDR2 SDRAM Controller with AltMemPHY IP"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Memory Interfaces and Controllers/Memory Interfaces with AltMemPHY"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
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  <documentUrl
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 </component>
 <component
   name="alt_mem_if_civ_ddr2_phy"
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   displayName="DDR2 SDRAM phy"
   version="1.0.0"
   description="Memory Physical Layer - DDR2 SDRAM PHY for alt_mem_if"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
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  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
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  <tag2
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 </component>
 <component
   name="alt_mem_if_civ_ddr2_status_bridge"
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   version="1.0.0"
   description="EMIF Status Bridge for AltMemPHY"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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 <component
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 <component
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 </plugin>
 <plugin
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 <plugin
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 <plugin
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 <component
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 <component
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 <plugin
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 <plugin
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 <plugin
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 <component
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 <component
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 <component
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 <component
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 </component>
 <component
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   categories="Interface Protocols/Ethernet/10G to 1G Multi-rate Ethernet"
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  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria V /// Arria 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide (Arria 10)"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/nik1398707230472.html#joc1445401896251" />
  <documentUrl
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     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/nik1398984401269.html#joc1445401896251" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/nfa1442227610714.html" />
 </component>
 <component
   name="alt_mge_phy_pcs"
   file="ethernet/alt_mge_phy/alt_mge_phy_pcs_hw.tcl"
   displayName="1G/2.5G/5G/10G Multi-rate Ethernet PHY Soft PCS"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="alt_mge_phy_xcvr_term"
   file="ethernet/alt_mge_phy/alt_mge_phy_xcvr_term_hw.tcl"
   displayName="MGE PHY Transceiver Termination"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
 </component>
 <component
   name="alt_mge_rd_addrdec_mch_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G/rtl/address_decoder/alt_mge_rd_addrdec_mch_a10.qsys"
   displayName="alt_mge_rd_addrdec_mch_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_rd_addrdec_mch_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_10G/rtl/address_decoder/alt_mge_rd_addrdec_mch_a10.qsys"
   displayName="alt_mge_rd_addrdec_mch_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_rd_addrdec_mch_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_1588v2/rtl/address_decoder/alt_mge_rd_addrdec_mch_a10.qsys"
   displayName="alt_mge_rd_addrdec_mch_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_rd_avmm_mux_xcvr_rcfg_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G/rtl/address_decoder/alt_mge_rd_avmm_mux_xcvr_rcfg_a10.qsys"
   displayName="alt_mge_rd_avmm_mux_xcvr_rcfg_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_rd_avmm_mux_xcvr_rcfg_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_10G/rtl/address_decoder/alt_mge_rd_avmm_mux_xcvr_rcfg_a10.qsys"
   displayName="alt_mge_rd_avmm_mux_xcvr_rcfg_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_rd_avmm_mux_xcvr_rcfg_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_1588v2/rtl/address_decoder/alt_mge_rd_avmm_mux_xcvr_rcfg_a10.qsys"
   displayName="alt_mge_rd_avmm_mux_xcvr_rcfg_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_atx_pll_10g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10G_USXGMII/rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g_a10.qsys"
   displayName="alt_mge_xcvr_atx_pll_10g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_atx_pll_10g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_10G/rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g_a10.qsys"
   displayName="alt_mge_xcvr_atx_pll_10g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_atx_pll_2p5g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G/rtl/pll_atxpll/alt_mge_xcvr_atx_pll_2p5g_a10.qsys"
   displayName="alt_mge_xcvr_atx_pll_2p5g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_atx_pll_2p5g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_10G/rtl/pll_atxpll/alt_mge_xcvr_atx_pll_2p5g_a10.qsys"
   displayName="alt_mge_xcvr_atx_pll_2p5g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_atx_pll_2p5g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_1588v2/rtl/pll_atxpll/alt_mge_xcvr_atx_pll_2p5g_a10.qsys"
   displayName="alt_mge_xcvr_atx_pll_2p5g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_fpll_1g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G/rtl/pll_fpll/alt_mge_xcvr_fpll_1g_a10.qsys"
   displayName="alt_mge_xcvr_fpll_1g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_fpll_1g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_10G/rtl/pll_fpll/alt_mge_xcvr_fpll_1g_a10.qsys"
   displayName="alt_mge_xcvr_fpll_1g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_fpll_1g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_1588v2/rtl/pll_fpll/alt_mge_xcvr_fpll_1g_a10.qsys"
   displayName="alt_mge_xcvr_fpll_1g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_reset_ctrl_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10G_USXGMII/rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel_a10.qsys"
   displayName="alt_mge_xcvr_reset_ctrl_channel_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_reset_ctrl_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G/rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel_a10.qsys"
   displayName="alt_mge_xcvr_reset_ctrl_channel_a10"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_reset_ctrl_channel_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_10G/rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel_a10.qsys"
   displayName="alt_mge_xcvr_reset_ctrl_channel_a10"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_reset_ctrl_channel_a10"
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   displayName="alt_mge_xcvr_reset_ctrl_channel_a10"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_reset_ctrl_txpll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10G_USXGMII/rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_txpll_a10.qsys"
   displayName="alt_mge_xcvr_reset_ctrl_txpll_a10"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_reset_ctrl_txpll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G/rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_txpll_a10.qsys"
   displayName="alt_mge_xcvr_reset_ctrl_txpll_a10"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_reset_ctrl_txpll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_2_5G_10G/rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_txpll_a10.qsys"
   displayName="alt_mge_xcvr_reset_ctrl_txpll_a10"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_mge_xcvr_reset_ctrl_txpll_a10"
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   displayName="alt_mge_xcvr_reset_ctrl_txpll_a10"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_ntrlkn_10l_6g"
   file="alt_interlaken/alt_ntrlkn_10l_6g/alt_ntrlkn_10l_6g_hw.tcl"
   displayName="altera_interlaken_10lane_6g"
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   description="Altera Interlaken"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="alt_ntrlkn_12l_10g"
   file="alt_interlaken/alt_ntrlkn_12l_10g/alt_ntrlkn_12l_10g_hw.tcl"
   displayName="altera_interlaken_12lane_10g"
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   description="Altera Interlaken"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="alt_ntrlkn_12l_6g"
   file="alt_interlaken/alt_ntrlkn_12l_6g/alt_ntrlkn_12l_6g_hw.tcl"
   displayName="altera_interlaken_12lane_6g"
   version="25.1"
   description="Altera Interlaken"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="alt_ntrlkn_20l_6g"
   file="alt_interlaken/alt_ntrlkn_20l_6g/alt_ntrlkn_20l_6g_hw.tcl"
   displayName="altera_interlaken_20lane_6g"
   version="25.1"
   description="Altera Interlaken"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="alt_ntrlkn_4l_3g"
   file="alt_interlaken/alt_ntrlkn_4l_3g/alt_ntrlkn_4l_3g_hw.tcl"
   displayName="altera_interlaken_4lane_3g"
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   description="Altera Interlaken"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="alt_ntrlkn_4l_6g"
   file="alt_interlaken/alt_ntrlkn_4l_6g/alt_ntrlkn_4l_6g_hw.tcl"
   displayName="altera_interlaken_4lane_6g"
   version="25.1"
   description="Altera Interlaken"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="alt_ntrlkn_8l_3g"
   file="alt_interlaken/alt_ntrlkn_8l_3g/alt_ntrlkn_8l_3g_hw.tcl"
   displayName="altera_interlaken_8lane_3g"
   version="25.1"
   description="Altera Interlaken"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="alt_ntrlkn_8l_6g"
   file="alt_interlaken/alt_ntrlkn_8l_6g/alt_ntrlkn_8l_6g_hw.tcl"
   displayName="altera_interlaken_8lane_6g"
   version="25.1"
   description="Altera Interlaken"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="alt_ntrlkn_hsio_bank_10g"
   file="alt_interlaken/altera_interlaken_hsio_bank/altera_interlaken_hsio_bank_10g/alt_ntrlkn_hsio_bank_10g_hw.tcl"
   displayName="alt_ntrlkn_hsio_bank_10g"
   version="25.1"
   description="Altera Interlaken HSIO Bank 10G"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="alt_ntrlkn_hsio_bank_bpcs4"
   file="alt_interlaken/altera_interlaken_hsio_bank/altera_interlaken_hsio_bank_bpcs4/alt_ntrlkn_hsio_bank_bpcs4_hw.tcl"
   displayName="alt_ntrlkn_hsio_bank_bpcs4"
   version="25.1"
   description="Altera Interlaken HSIO Bank 6G"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="alt_ntrlkn_hsio_bank_bpcs_3g"
   file="alt_interlaken/altera_interlaken_hsio_bank/altera_interlaken_hsio_bank_bpcs_3g/alt_ntrlkn_hsio_bank_bpcs_3g_hw.tcl"
   displayName="alt_ntrlkn_hsio_bank_bpcs_3g"
   version="25.1"
   description="Altera Interlaken HSIO Bank 3G"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="alt_ntrlkn_hsio_bank_pmad5"
   file="alt_interlaken/altera_interlaken_hsio_bank/altera_interlaken_hsio_bank_pmad5/alt_ntrlkn_hsio_bank_pmad5_hw.tcl"
   displayName="alt_ntrlkn_hsio_bank_pmad5"
   version="25.1"
   description="Altera Interlaken HSIO Bank 6G"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="alt_ntrlkn_oob_rx"
   file="alt_interlaken/alt_ntrlkn_oob/alt_ntrlkn_oob_rx/alt_ntrlkn_oob_rx_hw.tcl"
   displayName="alt_ntrlkn_oob_rx"
   version="25.1"
   description="Altera Interlaken Out of Band Flow Control for Receiver"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="alt_ntrlkn_oob_tx"
   file="alt_interlaken/alt_ntrlkn_oob/alt_ntrlkn_oob_tx/alt_ntrlkn_oob_tx_hw.tcl"
   displayName="alt_ntrlkn_oob_tx"
   version="25.1"
   description="Altera Interlaken Out of Band flow control for Transmitter"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="alt_ntrlkn_reset"
   file="alt_interlaken/alt_interlaken_rst/alt_ntrlkn_reset_hw.tcl"
   displayName="alt_ntrlkn_reset"
   version="25.1"
   description="Altera Interlaken RESET Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="alt_pr"
   file="alt_pr/alt_pr/alt_pr_hw.tcl"
   displayName="Partial Reconfiguration IP"
   version="25.1"
   description="Partial Reconfiguration megafunction is used to reconfigure part of your design while the rest  of your design continues to run."
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="HardCopy II /// APEX20K /// Cyclone V /// MAX9000 /// HardCopy III /// HardCopy IV /// Cyclone 10 LP /// EPC1 /// EPC2 /// eFPGA 28 HPM /// Programmer Dummy Family /// Cyclone IV E /// MAX V /// FLEX6000 /// Arria 10 /// Cyclone III LS /// FLEX10KE /// Soc Series V /// Stratix 10 for Emulator Use /// Arria II GX /// APEX II /// Arria II GZ /// Cyclone II /// FLEX10KB /// FLEX10KA /// Stratix /// MAX7000AE /// Stratix GX /// Cyclone III /// MAX3000A /// ALTERA /// Cyclone IV GX /// Enhanced Configuration Devices /// MAX 10 /// HardCopy Stratix /// MAX II /// Stratix III /// Arria V GZ /// MAX7000S /// Virtual JTAG TAP /// EMBEDDED_PROCESSOR /// ASC devices /// Cyclone /// Stratix II /// Stratix 10 /// FLEX10K /// FLEX8000 /// EXCALIBUR_ARM /// Stratix V /// MAX7000B /// MAX7000A /// ACEX1K /// APEX20KC /// Stratix II GX /// APEX20KE /// Arria GX /// Flash Memory /// Arria V /// None /// Mercury /// Stratix IV" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/mwh1393631425397.html" />
 </component>
 <component
   name="alt_sld_fab"
   file="sld/core/altera_instrumentation_fabric/alt_sld_fab_hw.tcl"
   displayName="Top level generated instrumentation fabric"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="SUPPRESS_WARNINGS" value="NO_PORTS_AFTER_ELABORATION" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="alt_usxgmii_phy_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10G_USXGMII/rtl/phy/alt_usxgmii_phy_a10.qsys"
   displayName="alt_usxgmii_phy_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_vip_avst_video_monitor"
   file="sld/trace/monitors/alt_vip_avst_video_monitor/alt_vip_avst_video_monitor_hw.tcl"
   displayName="Avalon-ST Video Monitor Intel FPGA IP"
   version="25.1"
   description="Monitors an Avalon-ST Video connection to facilitate debug of a video system. Data is captured from the datapath and exposed via one or more Avalon-ST source interfaces"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=false"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="snoop_composition_callback" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <tag2 key="VALIDATION_CALLBACK" value="snoop_validation_callback" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <component
   name="alt_vip_bps_converter"
   file="vip/ip_library/component_ip/utility/alt_vip_bps_converter/alt_vip_bps_converter_hw.tcl"
   displayName="Bits per Symbol converter"
   version="25.1"
   description="Convert Bits per Symbol"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_cadence_detect"
   file="vip/ip_library/component_ip/processing/alt_vip_cadence_detect/alt_vip_cadence_detect_hw.tcl"
   displayName="Cadence Detect core"
   version="25.1"
   description="This receives cadence detect commands on the cmd interface and video data on the other two inputs and outputs cadence responses which a scheduler may receive and act upon."
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="cadence_detect_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_chroma_key_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_chroma_key_alg_core/alt_vip_chroma_key_alg_core_hw.tcl"
   displayName="chroma key algorithmic core"
   version="25.1"
   description="Sets Alpha value on top channel to predetermined number based upon channels 2 to 0 matching the key"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_cl_2dfir"
   file="vip/ip_library/full_ip/alt_vip_cl_2dfir/alt_vip_cl_2dfir_hw.tcl"
   displayName="2D-FIR II (4K ready)"
   version="25.1"
   description="Applies a 2D FIR filter to the incoming video frames"
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_cb" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <plugin
   name="alt_vip_cl_2dfir_driver"
   file="vip/ip_library/full_ip/alt_vip_cl_2dfir/alt_vip_cl_2dfir_sw.tcl"
   displayName="alt_vip_cl_2dfir_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_2dfir"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="alt_vip_cl_clp"
   file="vip/ip_library/full_ip/alt_vip_cl_clp/alt_vip_cl_clp_hw.tcl"
   displayName="Clipper II (4K Ready)"
   version="25.1"
   description="The Clipper II clips a specified portion from an input video field."
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="clp_composition_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="clp_validation_callback" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <plugin
   name="alt_vip_cl_clp_driver"
   file="vip/ip_library/full_ip/alt_vip_cl_clp/alt_vip_cl_clp_sw.tcl"
   displayName="alt_vip_cl_clp_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_clp"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="alt_vip_cl_cps"
   file="vip/ip_library/full_ip/alt_vip_cl_cps/alt_vip_cl_cps_hw.tcl"
   displayName="Color Plane Sequencer II (4K Ready)"
   version="25.1"
   description="The Color Plane Sequencer changes how color planes are transmitted across the Avalon-ST Video interface. It can also combine two streams into one or split/duplicate a stream into two."
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="cps_composition_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="cps_validation_callback" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <component
   name="alt_vip_cl_crs"
   file="vip/ip_library/full_ip/alt_vip_cl_crs/alt_vip_cl_crs_hw.tcl"
   displayName="Chroma Resampler II (4K Ready)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_cb" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <component
   name="alt_vip_cl_crs_422_to_var"
   file="vip/ip_library/full_ip/alt_vip_cl_crs/alt_vip_cl_crs_422_to_var_hw.tcl"
   displayName="Chroma Resampler (4:2:2 to variable)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_cb" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <component
   name="alt_vip_cl_crs_444_to_var"
   file="vip/ip_library/full_ip/alt_vip_cl_crs/alt_vip_cl_crs_444_to_var_hw.tcl"
   displayName="Chroma Resampler (4:4:4 to variable)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_cb" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <plugin
   name="alt_vip_cl_crs_driver"
   file="vip/ip_library/full_ip/alt_vip_cl_crs/alt_vip_cl_crs_sw.tcl"
   displayName="alt_vip_cl_crs_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_crs"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="alt_vip_cl_crs_var_to_422"
   file="vip/ip_library/full_ip/alt_vip_cl_crs/alt_vip_cl_crs_var_to_422_hw.tcl"
   displayName="Chroma Resampler (variable to 4:2:2)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_cb" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
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     type="OTHER"
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 </component>
 <component
   name="alt_vip_cl_crs_var_to_444"
   file="vip/ip_library/full_ip/alt_vip_cl_crs/alt_vip_cl_crs_var_to_444_hw.tcl"
   displayName="Chroma Resampler (variable to 4:4:4)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_cb" />
  <tag2
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  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
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     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <component
   name="alt_vip_cl_csc"
   file="vip/ip_library/full_ip/alt_vip_cl_csc/alt_vip_cl_csc_hw.tcl"
   displayName="Color Space Converter II (4K Ready)"
   version="25.1"
   description="The CSC converts between color spaces using either predefined settings or user specified coefficients."
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
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  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <plugin
   name="alt_vip_cl_csc.qprs"
   file="vip/ip_library/full_ip/alt_vip_cl_csc/alt_vip_cl_csc.qprs"
   displayName="alt_vip_cl_csc.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
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 </plugin>
 <plugin
   name="alt_vip_cl_csc_driver"
   file="vip/ip_library/full_ip/alt_vip_cl_csc/alt_vip_cl_csc_sw.tcl"
   displayName="alt_vip_cl_csc_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_csc"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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   name="alt_vip_cl_cvi"
   file="vip/ip_library/full_ip/alt_vip_cl_cvi/alt_vip_cl_cvi_hw.tcl"
   displayName="Clocked Video Input II (4K Ready)"
   version="25.1"
   description="The Clocked Video Input II converts standard video formats such as BT656 and VGA to Avalon-ST Video."
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
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 <plugin
   name="alt_vip_cl_cvi.qprs"
   file="vip/ip_library/full_ip/alt_vip_cl_cvi/alt_vip_cl_cvi.qprs"
   displayName="alt_vip_cl_cvi.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
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 <plugin
   name="alt_vip_cl_cvi_driver"
   file="vip/ip_library/full_ip/alt_vip_cl_cvi/alt_vip_cl_cvi_sw.tcl"
   displayName="alt_vip_cl_cvi_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_cvi"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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   name="alt_vip_cl_cvo"
   file="vip/ip_library/full_ip/alt_vip_cl_cvo/alt_vip_cl_cvo_hw.tcl"
   displayName="Clocked Video Output II (4K Ready)"
   version="25.1"
   description="The Clocked Video Output converts Avalon-ST Video to standard video formats such as BT656 or VGA."
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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     type="OTHER"
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  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <plugin
   name="alt_vip_cl_cvo.qprs"
   file="vip/ip_library/full_ip/alt_vip_cl_cvo/alt_vip_cl_cvo.qprs"
   displayName="alt_vip_cl_cvo.qprs"
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   description=""
   tags=""
   categories=""
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   name="alt_vip_cl_cvo_driver"
   file="vip/ip_library/full_ip/alt_vip_cl_cvo/alt_vip_cl_cvo_sw.tcl"
   displayName="alt_vip_cl_cvo_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_cvo"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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   name="alt_vip_cl_dil"
   file="vip/ip_library/full_ip/alt_vip_cl_dil/alt_vip_cl_dil_hw.tcl"
   displayName="Deinterlacer II (4K HDR passthrough)"
   version="25.1"
   description="Please refer to the user-guide for details of new CSR registers that now make Deinterlacer II easier to setup and tune for best QOR in non-VOF modes.  Note that 4K passthrough is supported in some modes, but not all, as detailed in the user guide.  For 4K passthrough in unsupported configurations, a pair of Switch II IP cores either side of the Deinterlacer II will provide the 4K passthrough feature. "
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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     type="OTHER"
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
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 <plugin
   name="alt_vip_cl_dil_driver"
   file="vip/ip_library/full_ip/alt_vip_cl_dil/alt_vip_cl_dil_sw.tcl"
   displayName="alt_vip_cl_dil_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_dil"
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   type="com.altera.entityinterfaces.IElementClass"
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   name="alt_vip_cl_fb_switch"
   file="vip/ip_library/full_ip/alt_vip_cl_fb_switch/alt_vip_cl_fb_switch_hw.tcl"
   displayName="Frame Buffer Shuffle"
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   description="Allows the ordering of a frame buffer an another VIP core to be swapped at runtime"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <component
   name="alt_vip_cl_gamma_corrector"
   file="vip/ip_library/full_ip/alt_vip_cl_gamma_corrector/alt_vip_cl_gamma_corrector_hw.tcl"
   displayName="Gamma Corrector II (4K Ready)"
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   description=""
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <plugin
   name="alt_vip_cl_gamma_corrector_driver"
   file="vip/ip_library/full_ip/alt_vip_cl_gamma_corrector/alt_vip_cl_gamma_corrector_sw.tcl"
   displayName="alt_vip_cl_gamma_corrector_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_gamma_corrector"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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   name="alt_vip_cl_guard_bands"
   file="vip/ip_library/full_ip/alt_vip_cl_guard_bands/alt_vip_cl_guard_bands_hw.tcl"
   displayName="Configurable Guard Bands (4K Ready)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="gb_composition_callback" />
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     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
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     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <component
   name="alt_vip_cl_interlacer"
   file="vip/ip_library/full_ip/alt_vip_cl_interlacer/alt_vip_cl_interlacer_hw.tcl"
   displayName="Interlacer II (4K Ready)"
   version="25.1"
   description="The Interlacer II interlaces progressive frames to create a stream of alternating F0 and F1 fields."
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="interlacer_composition_callback" />
  <tag2
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     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <plugin
   name="alt_vip_cl_interlacer_driver"
   file="vip/ip_library/full_ip/alt_vip_cl_interlacer/alt_vip_cl_interlacer_sw.tcl"
   displayName="alt_vip_cl_interlacer_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_interlacer"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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 <component
   name="alt_vip_cl_mixer"
   file="vip/ip_library/full_ip/alt_vip_cl_mixer/alt_vip_cl_mixer_hw.tcl"
   displayName="Mixer II (4K Ready)"
   version="25.1"
   description="The Mixer II integrates a test pattern generator, which outputs either a continual color bar or uniform test pattern at the required frame resolution."
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_callback" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade_callback" />
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     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
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  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <plugin
   name="alt_vip_cl_mixer_driver"
   file="vip/ip_library/full_ip/alt_vip_cl_mixer/alt_vip_cl_mixer_sw.tcl"
   displayName="alt_vip_cl_mixer_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_mixer"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="alt_vip_cl_packet_closer"
   file="vip/ip_library/full_ip/alt_vip_cl_packet_closer/alt_vip_cl_packet_closer_hw.tcl"
   displayName="Packet Timeout Controller"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
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  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
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     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <component
   name="alt_vip_cl_packet_dangler"
   file="vip/ip_library/full_ip/alt_vip_cl_packet_dangler/alt_vip_cl_packet_dangler_hw.tcl"
   displayName="Packet Timeout Creator"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
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   file="vip/ip_library/full_ip/alt_vip_cl_pip_conv/alt_vip_cl_pip_conv_hw.tcl"
   displayName="Pixels in Parallel Convertor"
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   description=""
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing"
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   file="vip/ip_library/full_ip/alt_vip_cl_scl/alt_vip_cl_scl_hw.tcl"
   displayName="Scaler II (4K Ready)"
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   description="The Scaler II up-scales or down-scales video fields using nearest neighbour, biliner, bicubic, polyphase or edge adaptive algorithms."
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   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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   displayName="alt_vip_cl_scl_driver"
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   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_scl"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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   name="alt_vip_cl_stream_cleaner"
   file="vip/ip_library/full_ip/alt_vip_cl_stream_cleaner/alt_vip_cl_stream_cleaner_hw.tcl"
   displayName="Avalon-ST Video Stream Cleaner"
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   description=""
   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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     type="OTHER"
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   displayName="alt_vip_cl_stream_cleaner_driver"
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   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_stream_cleaner"
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   file="vip/ip_library/full_ip/alt_vip_cl_swi/alt_vip_cl_swi_hw.tcl"
   displayName="Switch II (4K Ready)"
   version="25.1"
   description="The Video Switch"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon,clock,interrupt"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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   file="vip/ip_library/full_ip/alt_vip_cl_swi/alt_vip_cl_swi_sw.tcl"
   displayName="alt_vip_cl_swi_driver"
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   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_swi"
   categories="driver_element"
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   file="vip/ip_library/full_ip/alt_vip_cl_tpg/alt_vip_cl_tpg_hw.tcl"
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   description="The Test Pattern Generator generates video fields with various patterns according to the specifications of the Avalon-ST Video protocol."
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   categories="DSP/Video and Image Processing"
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     type="OTHER"
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 <plugin
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   file="vip/ip_library/full_ip/alt_vip_cl_tpg/alt_vip_cl_tpg_sw.tcl"
   displayName="alt_vip_cl_tpg_driver"
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   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_tpg"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
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   file="vip/ip_library/full_ip/alt_vip_cl_vfb/alt_vip_cl_vfb_hw.tcl"
   displayName="Frame Buffer II (4K Ready)"
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   tags="AUTHORSHIP=Intel Corporation"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
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   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=alt_vip_cl_vfb"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
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   file="vip/ip_library/component_ip/processing/alt_vip_clipper_alg_core/alt_vip_clipper_alg_core_hw.tcl"
   displayName="Clipper Algorithmic Core"
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   categories="DSP/Video and Image Processing/Component Library"
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   file="vip/ip_library/component_ip/schedulers/alt_vip_clipper_scheduler/alt_vip_clipper_scheduler_hw.tcl"
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   categories="DSP/Video and Image Processing/Component Library"
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 <component
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   file="vip/ip_library/component_ip/utility/alt_vip_control_slave/alt_vip_control_slave_hw.tcl"
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   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
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 <component
   name="alt_vip_cpp_converter"
   file="vip/ip_library/component_ip/utility/alt_vip_cpp_converter/alt_vip_cpp_converter_hw.tcl"
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   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
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 <component
   name="alt_vip_cps_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_cps_alg_core/alt_vip_cps_alg_core_hw.tcl"
   displayName="CPS Algorithmic Core"
   version="25.1"
   description="Forward/merge incoming packets, rearranging/cropping/duplicating color planes for one or two outputs"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
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 <component
   name="alt_vip_cps_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_cps_scheduler/alt_vip_cps_scheduler_hw.tcl"
   displayName="CPS Scheduler"
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   description="Schedule the routing of packets in the cps core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
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  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_crs_422_drop_pad"
   file="vip/ip_library/component_ip/processing/alt_vip_crs_422_drop_pad/alt_vip_crs_422_drop_pad_hw.tcl"
   displayName="Chroma resampler 4:2:2 colours per pixel adapter"
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   description="Adds or removes an unused symbol per pixel for 4:2:2 on a variable colour space interface"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
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 </component>
 <component
   name="alt_vip_crs_h_down_core"
   file="vip/ip_library/component_ip/processing/alt_vip_crs_h_down_core/alt_vip_crs_h_down_core_hw.tcl"
   displayName="Chroma resampler core: 4:4:4 to 4:2:2"
   version="25.1"
   description="Downsamples 4:4:4 video lines to 4:2:2"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
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  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_crs_h_up_core"
   file="vip/ip_library/component_ip/processing/alt_vip_crs_h_up_core/alt_vip_crs_h_up_core_hw.tcl"
   displayName="Chroma resampler core: 4:2:2 to 4:4:4"
   version="25.1"
   description="Upsamples 4:2:2 video lines to 4:4:4"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
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  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_crs_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_crs_scheduler/alt_vip_crs_scheduler_hw.tcl"
   displayName="CRS Scheduler"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
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  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_crs_v_down_core"
   file="vip/ip_library/component_ip/processing/alt_vip_crs_v_down_core/alt_vip_crs_v_down_core_hw.tcl"
   displayName="Chroma resampler core: 4:2:2 to 4:2:0"
   version="25.1"
   description="Downsamples 4:2:2 video lines to 4:2:0"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_crs_v_up_core"
   file="vip/ip_library/component_ip/processing/alt_vip_crs_v_up_core/alt_vip_crs_v_up_core_hw.tcl"
   displayName="Chroma resampler core: 4:2:0 to 4:2:2"
   version="25.1"
   description="Upsamples 4:2:0 video lines to 4:2:2"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_csc_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_csc_alg_core/alt_vip_csc_alg_core_hw.tcl"
   displayName="CSC Algorithmic Core"
   version="25.1"
   description="Converts between color spaces"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
 </component>
 <component
   name="alt_vip_csc_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_csc_scheduler/alt_vip_csc_scheduler_hw.tcl"
   displayName="CSC Scheduler"
   version="25.1"
   description="Optional scheduler for the CSC. Used for user-packet support and coefficient updates at run-time"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_custom_reset_synchronizer"
   file="vip/ip_library/component_ip/utility/alt_vip_custom_reset_synchronizer/alt_vip_custom_reset_synchronizer_hw.tcl"
   displayName="Custom Reset Synchronizer"
   version="25.1"
   description="Reset synchronizer that will synchronize an input reset and output a reset that deasserts synchronously and asserts asynchronous/synchronously."
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="alt_vip_cvi_core"
   file="vip/ip_library/component_ip/alt_vip_cvi_core/alt_vip_cvi_core_hw.tcl"
   displayName="alt_vip_cvi_core"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="cvi_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_cvo_core"
   file="vip/ip_library/component_ip/alt_vip_cvo_core/alt_vip_cvo_core_hw.tcl"
   displayName="Clocked Video Output Core"
   version="25.1"
   description="The Clocked Video Output converts Avalon-ST Video to standard video formats such as BT656 or VGA."
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="cvo_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_cvo_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_cvo_scheduler/alt_vip_cvo_scheduler_hw.tcl"
   displayName="CVO scheduler"
   version="25.1"
   description="Scheduler for the CVO component"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_dil_algorithm"
   file="vip/ip_library/component_ip/processing/alt_vip_dil_algorithm/alt_vip_dil_algorithm_hw.tcl"
   displayName="Deinterlace algorithmic core"
   version="25.1"
   description="Receives deinterlace commands (on the cmd interface), reads the video data on the bob, weave and motion interfaces and sources deinterlaced video on dout interface"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="dil_algo_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_dil_bob_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_dil_bob_scheduler/alt_vip_dil_bob_scheduler_hw.tcl"
   displayName="Deinterlacer bob scheduler"
   version="25.1"
   description="Scheduler for the bob deinterlacer core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_dil_low_angle_algorithm"
   file="vip/ip_library/component_ip/processing/alt_vip_dil_low_angle_algorithm/alt_vip_dil_low_angle_algorithm_hw.tcl"
   displayName="Deinterlace algorithmic core (high quality)"
   version="25.1"
   description="Receives deinterlace commands (on the cmd interface), reads the video data on the bob, weave and motion interfaces and sources deinterlaced video on dout interface"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="dil_algo_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_dil_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_dil_scheduler/alt_vip_dil_scheduler_hw.tcl"
   displayName="Deinterlacer scheduler"
   version="25.1"
   description="Scheduler for the deinterlacer core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="dil_scheduler_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_dil_sobel_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_dil_sobel_scheduler/alt_vip_dil_sobel_scheduler_hw.tcl"
   displayName="Deinterlacer scheduler"
   version="25.1"
   description="Scheduler for the HQ Sobel deinterlacer core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="dil_scheduler_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_dil_vof_scheduler"
   file="vip/ip_library/component_ip/alt_vip_dil_vof_scheduler/alt_vip_dil_vof_scheduler_hw.tcl"
   displayName="Broadcast Deinterlacer scheduler"
   version="25.1"
   description="Scheduler for the Broadcast deinterlacer core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="dil_scheduler_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_dil_weave_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_dil_weave_scheduler/alt_vip_dil_weave_scheduler_hw.tcl"
   displayName="Deinterlacer scheduler"
   version="25.1"
   description="Scheduler for the deinterlacer core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_fb_switch_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_fb_switch_scheduler/alt_vip_fb_switch_scheduler_hw.tcl"
   displayName="Frame Buffer Shuffle Scheduer"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="fbs_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_fir_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_fir_alg_core/alt_vip_fir_alg_core_hw.tcl"
   displayName="FIR Algorithmic Core"
   version="25.1"
   description="This block filters a line of data using either a standard 2D FIR Filter or an edge adaptive sharpening filter"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="fir_alg_core_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="fir_alg_core_validation_callback" />
 </component>
 <component
   name="alt_vip_fir_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_fir_scheduler/alt_vip_fir_scheduler_hw.tcl"
   displayName="FIR Scheduler"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="fir_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="fir_validation_callback" />
 </component>
 <component
   name="alt_vip_gamma_corrector_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_gamma_corrector_alg_core/alt_vip_gamma_corrector_alg_core_hw.tcl"
   displayName="Gamma Corrector Algorithmic Core"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="gamma_corrector_alg_core_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="gamma_corrector_alg_core_validation_callback" />
 </component>
 <component
   name="alt_vip_gamma_corrector_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_gamma_corrector_scheduler/alt_vip_gamma_corrector_scheduler_hw.tcl"
   displayName="Gamma Corrector Scheduler"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_guard_bands_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_guard_bands_alg_core/alt_vip_guard_bands_alg_core_hw.tcl"
   displayName="Guard bands core"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="gb_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="gb_validation_callback" />
 </component>
 <component
   name="alt_vip_guard_bands_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_guard_bands_scheduler/alt_vip_guard_bands_scheduler_hw.tcl"
   displayName="Gaurd Band Scheduler"
   version="25.1"
   description="Optional scheduler for the Gaurd Band VIP core. Used for user-packet support and min/max updates at run-time"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_horiz_scaler_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_horiz_scaler_alg_core/alt_vip_horiz_scaler_alg_core_hw.tcl"
   displayName="Horizontal Scaler Algorithmic Core"
   version="25.1"
   description="This block scales a line of video data using bilinear, bicubic or polyphase algorithms according
	o a scaling ratio defined through the Avalon-ST Message Command port"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="horiz_scl_alg_core_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="horiz_scl_alg_core_validation_callback" />
 </component>
 <component
   name="alt_vip_interlacer_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_interlacer_scheduler/alt_vip_interlacer_scheduler_hw.tcl"
   displayName="Interlacer Scheduler"
   version="25.1"
   description="Scheduler for the interlacer"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_line_buffer"
   file="vip/ip_library/component_ip/utility/alt_vip_line_buffer/alt_vip_line_buffer_hw.tcl"
   displayName="Video Line Buffer"
   version="25.1"
   description="This block receives lines of video data on its Avalon-ST Message Data sink,
stores them and outputs kernels of lines through one or more Avalon-ST Message Data sources.
Operations are controlled through an Avalon-ST Message Command sink"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="line_buffer_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="line_buffer_validation_callback" />
 </component>
 <component
   name="alt_vip_line_stats"
   file="vip/ip_library/component_ip/utility/alt_vip_line_stats/alt_vip_line_stats_hw.tcl"
   displayName="Line Statistics block"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_message_sink_terminator"
   file="vip/ip_library/component_ip/utility/alt_vip_message_sink_terminator/alt_vip_message_sink_terminator_hw.tcl"
   displayName="Avalon-ST Message sink terminator"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="sink_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_message_width_adapt"
   file="vip/ip_library/component_ip/utility/alt_vip_message_width_adapt/alt_vip_message_width_adapt_hw.tcl"
   displayName="Avalon-ST Message Width Adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="adapt_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="adapt_validation_callback" />
 </component>
 <component
   name="alt_vip_mix_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_mix_alg_core/alt_vip_mix_alg_core_hw.tcl"
   displayName="Mixer algorithmic core"
   version="25.1"
   description="Receives mix commands (on the cmd interface), sources mixed video on dout interface"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_mix_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_mix_scheduler/alt_vip_mix_scheduler_hw.tcl"
   displayName="Mixer scheduler"
   version="25.1"
   description="Scheduler for the mixer component"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_mixer_alpha_merge"
   file="vip/ip_library/component_ip/utility/alt_vip_mixer_alpha_merge/alt_vip_mixer_alpha_merge_hw.tcl"
   displayName="Adds an alpha channel (if required) to a video stream."
   version="25.1"
   description="Adds an alpha channel (if required) to a video stream."
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_motion_detect"
   file="vip/ip_library/component_ip/processing/alt_vip_motion_detect/alt_vip_motion_detect_hw.tcl"
   displayName="Motion detect core"
   version="25.1"
   description="Receives motion detect commands (on the cmd interface), reads the video data on the video and motion interfaces and sources motion vectors on the motion and dout interfaces"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="motion_detect_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_packet_demux"
   file="vip/ip_library/component_ip/utility/alt_vip_packet_demux/alt_vip_packet_demux_hw.tcl"
   displayName="Packet Demux"
   version="25.1"
   description="Forward incoming packets to one of (up to) 21 outputs"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="demux_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="demux_validation_callback" />
 </component>
 <component
   name="alt_vip_packet_duplicator"
   file="vip/ip_library/component_ip/utility/alt_vip_packet_duplicator/alt_vip_packet_duplicator_hw.tcl"
   displayName="Packet Duplicator"
   version="25.1"
   description="Forward incoming packets, duplicating them for multiple recipients when requested"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="duplicator_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="duplicator_validation_callback" />
 </component>
 <component
   name="alt_vip_packet_mux"
   file="vip/ip_library/component_ip/utility/alt_vip_packet_mux/alt_vip_packet_mux_hw.tcl"
   displayName="Packet Mux"
   version="25.1"
   description="Mux up to 21 incoming streams of Avalon-ST packets"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="mux_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="mux_validation_callback" />
 </component>
 <component
   name="alt_vip_packet_transfer"
   file="vip/ip_library/component_ip/utility/alt_vip_packet_transfer/alt_vip_packet_transfer_hw.tcl"
   displayName="Packet Transfer"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="packet_transfer_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="packet_transfer_validation_callback" />
 </component>
 <component
   name="alt_vip_pip_converter_core"
   file="vip/ip_library/component_ip/utility/alt_vip_pip_converter_core/alt_vip_pip_converter_core_hw.tcl"
   displayName="Pixels in parallel converter core"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="pip_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_pip_sop_realign"
   file="vip/ip_library/component_ip/utility/alt_vip_pip_sop_realign/alt_vip_pip_sop_realign_hw.tcl"
   displayName="Pixels in parallel SOP realign"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="pip_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_scaler_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_scaler_alg_core/alt_vip_scaler_alg_core_hw.tcl"
   displayName="Scaler Algorithmic Core"
   version="25.1"
   description="This block scales a line of video data using bilinear, bicubic or polyphase algorithms according
	o a scaling ratio defined through the Avalon-ST Message Command port"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="scl_alg_core_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="scl_alg_core_validation_callback" />
 </component>
 <component
   name="alt_vip_scaler_kernel_creator"
   file="vip/ip_library/component_ip/processing/alt_vip_scaler_kernel_creator/alt_vip_scaler_kernel_creator_hw.tcl"
   displayName="Scaler Kernel Creator"
   version="25.1"
   description="This block calculates the kernel center lines required to produce each output line in an
uscaled or downscaled image, as well as bilinear errors or bicubic/polyphase phase numbers where required"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="kc_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="kc_validation_callback" />
 </component>
 <component
   name="alt_vip_scaler_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_scaler_scheduler/alt_vip_scaler_scheduler_hw.tcl"
   displayName="Scaler Scheduler"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="scl_sched_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="scl_sched_validation_callback" />
 </component>
 <component
   name="alt_vip_seq_par_convert"
   file="vip/ip_library/component_ip/utility/alt_vip_seq_par_convert/alt_vip_seq_par_convert_hw.tcl"
   displayName="Symbols in sequence/parallel converter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="seq_par_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_stream_cleaner_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_stream_cleaner_alg_core/alt_vip_stream_cleaner_alg_core_hw.tcl"
   displayName="Stream cleaner Alg core"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_stream_cleaner_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_stream_cleaner_scheduler/alt_vip_stream_cleaner_scheduler_hw.tcl"
   displayName="Stream cleaner scheduler"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_tpg_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_tpg_alg_core/alt_vip_tpg_alg_core_hw.tcl"
   displayName="Test Pattern Generator Core"
   version="25.1"
   description="Generates video test pattern streams for validation and testing purposes"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="tpg_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_tpg_bars_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_tpg_bars_alg_core/alt_vip_tpg_bars_alg_core_hw.tcl"
   displayName="Test Pattern Generator Core (Colour Bars)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="tpg_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="tpg_validation_callback" />
 </component>
 <component
   name="alt_vip_tpg_const_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_tpg_const_alg_core/alt_vip_tpg_const_alg_core_hw.tcl"
   displayName="Test Pattern Generator Core (Constant colour)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="tpg_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="tpg_validation_callback" />
 </component>
 <component
   name="alt_vip_tpg_multi_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_tpg_multi_scheduler/alt_vip_tpg_multi_scheduler_hw.tcl"
   displayName="Test Pattern Generator Scheduler"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="tpg_sched_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_tpg_scheduler"
   file="vip/ip_library/component_ip/schedulers/alt_vip_tpg_scheduler/alt_vip_tpg_scheduler_hw.tcl"
   displayName="Test Pattern Generator Scheduler"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="tpg_sched_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_tpg_sdi_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_tpg_sdi_alg_core/alt_vip_tpg_sdi_alg_core_hw.tcl"
   displayName="Test Pattern Generator Core (SDI pathological)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="tpg_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="tpg_validation_callback" />
 </component>
 <component
   name="alt_vip_vert_scaler_alg_core"
   file="vip/ip_library/component_ip/processing/alt_vip_vert_scaler_alg_core/alt_vip_vert_scaler_alg_core_hw.tcl"
   displayName="Vertical Scaler Algorithmic Core"
   version="25.1"
   description="This block scales a line of video data using bilinear, bicubic or polyphase algorithms according
	o a scaling ratio defined through the Avalon-ST Message Command port"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="vert_scl_alg_core_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="vert_scl_alg_core_validation_callback" />
 </component>
 <component
   name="alt_vip_vfb_linebuf_ctrl"
   file="vip/ip_library/component_ip/utility/alt_vip_vfb_linebuf_ctrl/alt_vip_vfb_linebuf_ctrl_hw.tcl"
   displayName="Line-based Frame Buffer Controller"
   version="25.1"
   description="Controls frame buffer read and write sequencing"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="linebuf_ctrl_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_vfb_rd_ctrl"
   file="vip/ip_library/component_ip/utility/alt_vip_vfb_rd_ctrl/alt_vip_vfb_rd_ctrl_hw.tcl"
   displayName="Frame Buffer Read Controller"
   version="25.1"
   description="Controls read side of frame buffer"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="rd_ctrl_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_vfb_sync_ctrl"
   file="vip/ip_library/component_ip/utility/alt_vip_vfb_sync_ctrl/alt_vip_vfb_sync_ctrl_hw.tcl"
   displayName="Frame Buffer Sync Controller"
   version="25.1"
   description="Controls frame buffer read and write sequencing"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="sync_ctrl_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_vfb_wr_ctrl"
   file="vip/ip_library/component_ip/utility/alt_vip_vfb_wr_ctrl/alt_vip_vfb_wr_ctrl_hw.tcl"
   displayName="Frame Buffer Write Controller"
   version="25.1"
   description="Controls write side of frame buffer"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="wr_ctrl_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_vip_video_input_bridge"
   file="vip/ip_library/component_ip/processing/alt_vip_video_input_bridge/alt_vip_video_input_bridge_hw.tcl"
   displayName="Video Input Bridge"
   version="25.1"
   description="The Video input bridge processes input packets to send responses to the scheduler. Image packetss can be broken into line packets"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="vib_composition_callback" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="vib_validation_callback" />
 </component>
 <component
   name="alt_vip_video_input_bridge_cmd"
   file="vip/ip_library/component_ip/processing/alt_vip_video_input_bridge_cmd/alt_vip_video_input_bridge_cmd_hw.tcl"
   displayName="Command Input Bridge"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="cib_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="cib_validation_callback" />
 </component>
 <component
   name="alt_vip_video_input_bridge_resp"
   file="vip/ip_library/component_ip/processing/alt_vip_video_input_bridge_resp/alt_vip_video_input_bridge_resp_hw.tcl"
   displayName="Video Input Bridge (resp only)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="vib_resp_elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="vib_resp_validation_callback" />
 </component>
 <component
   name="alt_vip_video_output_bridge"
   file="vip/ip_library/component_ip/processing/alt_vip_video_output_bridge/alt_vip_video_output_bridge_hw.tcl"
   displayName="Video Output Bridge"
   version="25.1"
   description="The Video Output Bridge generates an Avalon-ST Video stream"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cb" />
 </component>
 <component
   name="alt_vip_video_over_film"
   file="vip/ip_library/component_ip/processing/alt_vip_video_over_film/alt_vip_video_over_film_hw.tcl"
   displayName="Video over film core"
   version="25.1"
   description="Receives motion detect and VOF commands (on the cmd interface), reads the video data on the video and motion interfaces and sources motion vectors on the motion and dout interfaces"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing/Component Library"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_cb" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="alt_xcvr_12_bus_split"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_12_bus_split/alt_xcvr_12_bus_split_hw.tcl"
   displayName="Design Example 1:2 bus splitter (uneven)"
   version="16.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_12_bus_split_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_12_bus_split_val_callback" />
 </component>
 <component
   name="alt_xcvr_21_bus_concat"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_21_bus_concat/alt_xcvr_21_bus_concat_hw.tcl"
   displayName="Design Example 1:2 bus splitter (uneven)"
   version="16.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_21_bus_concat_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_21_bus_concat_val_callback" />
 </component>
 <component
   name="alt_xcvr_atx_tester"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_atx_tester/alt_xcvr_atx_tester_hw.tcl"
   displayName="ATX PLL Tester"
   version="14.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="alt_xcvr_atx_tester_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_atx_tester_val_callback" />
 </component>
 <component
   name="alt_xcvr_basic_custom_tester"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_basic_custom_tester/alt_xcvr_basic_custom_tester_hw.tcl"
   displayName="Basic/Custom 8G Tester"
   version="14.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_basic_custom_tester_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="alt_xcvr_basic_custom_tester_val_callback" />
 </component>
 <component
   name="alt_xcvr_bit_slip"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_bit_slip/alt_xcvr_bit_slip_hw.tcl"
   displayName="Design Example Bit Slip"
   version="14.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="alt_xcvr_bit_slip_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_bit_slip_val_callback" />
 </component>
 <component
   name="alt_xcvr_bitrev_byterev_polinv"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_bitrev_byterev_polinv/alt_xcvr_bitrev_byterev_polinv_hw.tcl"
   displayName="Design Example Double-Rate Mode Interface Adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_bitrev_byterev_polinv_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="alt_xcvr_bitrev_byterev_polinv_val_callback" />
 </component>
 <component
   name="alt_xcvr_bus_concat"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_bus_concat/alt_xcvr_bus_concat_hw.tcl"
   displayName="Bus Concat"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="alt_xcvr_bus_concat_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_bus_concat_val_callback" />
 </component>
 <component
   name="alt_xcvr_bus_splitter"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_bus_splitter/alt_xcvr_bus_splitter_hw.tcl"
   displayName="Bus Splitter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_bus_splitter_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_bus_splitter_val_callback" />
 </component>
 <component
   name="alt_xcvr_data_pattern_check"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_data_pattern_check/alt_xcvr_data_pattern_check_hw.tcl"
   displayName="Data Pattern Checker"
   version="15.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_data_pattern_check_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="alt_xcvr_data_pattern_check_val_callback" />
 </component>
 <component
   name="alt_xcvr_data_pattern_gen"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_data_pattern_gen/alt_xcvr_data_pattern_gen_hw.tcl"
   displayName="Data Pattern Generator"
   version="15.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_data_pattern_gen_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="alt_xcvr_data_pattern_gen_val_callback" />
 </component>
 <component
   name="alt_xcvr_ext_loopback"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_ext_loopback/alt_xcvr_ext_loopback_hw.tcl"
   displayName="Transceiver External Loopback"
   version="14.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_ext_loopback_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_ext_loopback_val_callback" />
 </component>
 <component
   name="alt_xcvr_freq_checker"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_freq_checker/alt_xcvr_freq_checker_hw.tcl"
   displayName="Design Example Frequency Checker"
   version="14.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_freq_checker_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_freq_checker_val_callback" />
 </component>
 <component
   name="alt_xcvr_if_adapter"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_if_adapter/alt_xcvr_if_adapter_hw.tcl"
   displayName="Conduit adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="alt_xcvr_if_adapter_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_if_adapter_val_callback" />
 </component>
 <component
   name="alt_xcvr_if_fanout"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_if_fanout/alt_xcvr_if_fanout_hw.tcl"
   displayName="Conduit Fanout"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="alt_xcvr_if_fanout_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_if_fanout_val_callback" />
 </component>
 <component
   name="alt_xcvr_if_terminator"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_if_terminator/alt_xcvr_if_terminator_hw.tcl"
   displayName="Conduit terminator"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_if_terminator_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_if_terminator_val_callback" />
 </component>
 <component
   name="alt_xcvr_pipe_phy_mac"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_pipe_phy_mac/alt_xcvr_pipe_phy_mac/alt_xcvr_pipe_phy_mac_hw.tcl"
   displayName="PCIe PIPE PHY Mac"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::alt_xcvr_pipe_phy_mac::alt_xcvr_pipe_phy_mac_elab_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="::alt_xcvr_pipe_phy_mac::alt_xcvr_pipe_phy_mac_val_callback" />
 </component>
 <component
   name="alt_xcvr_prbs_check"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_prbs_check/alt_xcvr_prbs_check_hw.tcl"
   displayName="PRBS Checker"
   version="14.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="alt_xcvr_prbs_check_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_prbs_check_val_callback" />
 </component>
 <component
   name="alt_xcvr_prbs_gen"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_prbs_gen/alt_xcvr_prbs_gen_hw.tcl"
   displayName="Design Example PRBS Generator"
   version="14.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="alt_xcvr_prbs_gen_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_prbs_gen_val_callback" />
 </component>
 <component
   name="alt_xcvr_reconfig"
   file="alt_xcvr_reconfig/alt_xcvr_reconfig/alt_xcvr_reconfig_hw.tcl"
   displayName="Transceiver Reconfiguration Controller IP"
   version="19.1"
   description="Transceiver Reconfiguration Controller is used to dynamically calibrate and reconfigure features of PHY IP cores"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V GZ /// Arria V /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1398984401269/nik1398984264716" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698037114" />
 </component>
 <component
   name="alt_xcvr_reconfig_cpu"
   file="alt_xcvr_reconfig/alt_xcvr_reconfig_soc/alt_xcvr_reconfig_cpu.qsys"
   displayName="alt_xcvr_reconfig_cpu"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="alt_xcvr_reconfig_cpu_ctrl_if"
   file="alt_xcvr_reconfig/alt_xcvr_reconfig_soc/alt_xcvr_reconfig_cpu_ctrl_if_hw.tcl"
   displayName="Reconfiguration Interface Control"
   version="11.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Transceiver Reconfiguration Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="false" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="alt_xcvr_reconfig_cpu_ram_if"
   file="alt_xcvr_reconfig/alt_xcvr_reconfig_soc/alt_xcvr_reconfig_cpu_ram_if_hw.tcl"
   displayName="alt_xcvr_reconfig_cpu_ram_if"
   version="11.0"
   description="Interface to external memory for alt_xcvr_reconfig_cpu"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Transceiver Reconfiguration Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="false" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="alt_xcvr_reset_sync"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_reset_sync/alt_xcvr_reset_sync_hw.tcl"
   displayName="Reset Synchronizer"
   version="14.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="alt_xcvr_reset_sync_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_reset_sync_val_callback" />
 </component>
 <component
   name="alt_xcvr_sc_debug"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_sc_debug/alt_xcvr_sc_debug_hw.tcl"
   displayName="System Console Debug block for hardware testing"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::alt_xcvr_sc_debug::alt_xcvr_sc_debug_elab_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="::alt_xcvr_sc_debug::alt_xcvr_sc_debug_val_callback" />
 </component>
 <component
   name="alt_xcvr_tb_stim_gen"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_tb_stim_gen/alt_xcvr_tb_stim_gen_hw.tcl"
   displayName="Design Example Testbech Stimulus Generator"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="alt_xcvr_tb_stim_gen_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="alt_xcvr_tb_stim_gen_val_callback" />
 </component>
 <component
   name="alt_xcvr_x1x2_if_adapter"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_x1x2_if_adapter/alt_xcvr_x1x2_if_adapter_hw.tcl"
   displayName="Design Example Double-Rate Mode Interface Adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="alt_xcvr_x1x2_if_adapter_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="alt_xcvr_x1x2_if_adapter_val_callback" />
 </component>
 <component
   name="altchip_id"
   file="altchip_id/source/altchip_id_hw.tcl"
   displayName="Unique Chip ID IP"
   version="25.1"
   description="The Unique Chip ID megafunction provides feature to acquire the unique chip ID of FPGA."
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="MAX 10 /// Cyclone V /// Arria V GZ /// Arria V /// Stratix V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683336/current/cores-user-guide.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683336/current/document-revision-history-for-the-chip.html" />
 </component>
 <component
   name="altclkctrl"
   file="megafunctions/altclkctrl/altclkctrl_hw.tcl"
   displayName="ALTCLKCTRL Intel FPGA IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation"
   categories="Basic Functions/Clocks; PLLs and Resets"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Stratix IV /// Stratix V /// MAX 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altclock.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_altclock.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697740509" />
 </component>
 <component
   name="altdq_dqs2"
   file="altdq_dqs2/altdq_dqs2_hw.tcl"
   displayName="ALTDQ_DQS2"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=true"
   categories="I/O"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="my_generate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <tag2 key="VALIDATION_CALLBACK" value="my_validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altdq_dqs2.pdf" />
 </component>
 <component
   name="altecc"
   file="megafunctions/altecc/altecc_hw.tcl"
   displayName="ALTECC IP"
   version="25.1"
   description="The ALTERA_ECC megafunction allows you to encoding or decoding input by using Hamming Coding Scheme"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Miscellaneous"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sam1395330298052/sam1395329715902" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_16550_uart"
   file="altera_16550_uart/altera_16550_uart_hw.tcl"
   displayName="16550 Compatible UART IP"
   version="25.1"
   description="UART with run-time configurability and 16550 compatible register space"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset"
   categories="Interface Protocols/Serial"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation" />
  <documentUrl displayName="DATASHEET" type="DATASHEET" url="http://www.altera.com" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1404147076304" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <plugin
   name="altera_16550_uart_driver"
   file="altera_16550_uart/altera_16550_uart_sw.tcl"
   displayName="altera_16550_uart_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_16550_uart"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_CORDIC"
   file="dsp/altera_CORDIC/source/altera_CORDIC_hw.tcl"
   displayName="ALTERA_CORDIC"
   version="25.1"
   description="A collection of fixed point CORDIC Functions"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade_callback" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="VHDL" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria V /// Arria V GZ /// Arria II GX /// Arria II GZ /// Cyclone 10 LP /// Cyclone V /// Cyclone IV E /// Cyclone IV GX /// MAX 10 /// Stratix V /// Stratix IV /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_input" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/eis1410764818924/eis1410936966508" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_a10_native_fixed_point_dsp"
   file="native_mac/twentynm_mac_native_hw/twentynm_mac_native_hw.tcl"
   displayName="Native Fixed Point DSP Intel Arria 10 FPGA IP"
   version="25.1"
   description="The NATIVE_DSP megafunction allows you to implement the primitive variable precision DSP block"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit"
   categories="DSP/Primitive DSP"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="parameter_upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_nfp_dsp.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/kly1418710866787/kly1415863279223" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_a10_xcvr_reset_sequencer"
   file="sld/misc/altera_a10_xcvr_reset_sequencer/altera_a10_xcvr_reset_sequencer_hw.tcl"
   displayName="Altera Arria 10 XCVR Reset Sequencer"
   version="25.1"
   description="Altera Arria 10 XCVR Reset Sequencer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="do_elaboration" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="HardCopy II /// APEX20K /// Cyclone V /// MAX9000 /// HardCopy III /// HardCopy IV /// Cyclone 10 LP /// EPC1 /// EPC2 /// eFPGA 28 HPM /// Programmer Dummy Family /// Cyclone IV E /// MAX V /// FLEX6000 /// Arria 10 /// Cyclone III LS /// FLEX10KE /// Soc Series V /// Stratix 10 for Emulator Use /// Arria II GX /// APEX II /// Arria II GZ /// Cyclone II /// FLEX10KB /// FLEX10KA /// Stratix /// MAX7000AE /// Stratix GX /// Cyclone III /// MAX3000A /// ALTERA /// Cyclone IV GX /// Enhanced Configuration Devices /// MAX 10 /// HardCopy Stratix /// MAX II /// Stratix III /// Arria V GZ /// MAX7000S /// Virtual JTAG TAP /// EMBEDDED_PROCESSOR /// ASC devices /// Cyclone /// Stratix II /// Stratix 10 /// FLEX10K /// FLEX8000 /// EXCALIBUR_ARM /// Stratix V /// MAX7000B /// MAX7000A /// ACEX1K /// APEX20KC /// Stratix II GX /// APEX20KE /// Arria GX /// Flash Memory /// Arria V /// None /// Mercury /// Stratix IV" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="altera_address_span_extender"
   file="merlin/altera_address_span_extender/altera_address_span_extender_hw.tcl"
   displayName="Address Span Extender"
   version="25.1"
   description="Creates a windowed bridge to allow masters to access a larger address map."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset"
   categories="Basic Functions/Bridges and Adaptors/Memory Mapped"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409959261007" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_adv_seu_detection"
   file="altera_adv_seu_detection/adv_seu_detection_hw.tcl"
   displayName="Advanced SEU Detection IP"
   version="25.1"
   description="Advanced SEU Detection provides features on error detection cyclical redundancy check  (EDCRC) and mitigating the impact of single event upset (SEU) on configuration RAM (CRAM)  array."
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
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  <documentUrl
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     type="OTHER"
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 </component>
 <component
   name="altera_arria10_chip_id"
   file="pgm/altera_arria10_chip_id/altera_arria10_chip_id_hw.tcl"
   displayName="Unique Chip ID IP"
   version="25.1"
   description="The Unique Chip ID IP megafunction provides feature to acquire the unique chip ID of FPGA."
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <documentUrl
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     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/sam1412052977775.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/rhs1517557757547.html" />
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 <component
   name="altera_arria10_hps"
   file="altera_hps/altera_hps_arria_10/hps/altera_hps_arria10_hw.tcl"
   displayName="Arria 10 Hard Processor System"
   version="25.1"
   description="The HPS contains a microprocessor unit (MPU) subsystem with dual-core ARM Cortex-A9 MPCore processors, flash memory controllers, dedicatedSDRAMcontroller interconnect, on-chip memories, support peripherals, interface peripherals, debug capabilities, and phase-locked loops (PLLs)."
   tags="AUTHORSHIP=Altera Corporation"
   categories="Processors and Peripherals/Hard Processor Systems"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
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     type="OTHER"
     url="http://www.altera.com/literature/lit-arria-10.jsp" />
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     type="OTHER"
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     type="OTHER"
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 </component>
 <component
   name="altera_arria10_hps_io"
   file="altera_hps/altera_hps_arria_10/hps_io/altera_hps_arria10_io_hw.tcl"
   displayName="altera_arria10_hps_io"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
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 </component>
 <component
   name="altera_arria10_interface_generator"
   file="altera_hps/altera_hps_arria_10/interface_generator/altera_arria10_interface_generator_hw.tcl"
   displayName="altera_arria10_interface_generator"
   version="14.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
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 </component>
 <component
   name="altera_asmi2_cmd_generator"
   file="pgm/altera_asmi_parallel2/qspi_cmd_generator/altera_asmi2_cmd_generator_hw.tcl"
   displayName="ASMI2 Command Generator"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
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  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_asmi2_csr_controller"
   file="pgm/altera_asmi_parallel2/csr_controller/altera_asmi2_csr_controller_hw.tcl"
   displayName="ASMI2 CSR Controller"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
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 <component
   name="altera_asmi2_qspi_interface"
   file="pgm/altera_asmi_parallel2/qspi_interface/altera_asmi2_qspi_interface_hw.tcl"
   displayName="ASMI2 QSPI Interface"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
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 </component>
 <component
   name="altera_asmi2_xip_controller"
   file="pgm/altera_asmi_parallel2/xip_controller/altera_asmi2_xip_controller_hw.tcl"
   displayName="ASMI2 XIP Controller"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
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  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_asmi_parallel"
   file="altera_asmi_parallel/altera_asmi_parallel_hw.tcl"
   displayName="ASMI Parallel IP"
   version="25.1"
   description="The ASMI Parallel megafunction provides access to erasable  programmable configurable serial (EPCS) and quad-serial configuration  (EPCQ) devices through parallel data input and output ports."
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation" />
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     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/sam1412044647169.html" />
 </component>
 <component
   name="altera_asmi_parallel2"
   file="pgm/altera_asmi_parallel2/asmi_top/altera_asmi_parallel2_hw.tcl"
   displayName="ASMI Parallel II Core IP"
   version="25.1"
   description="The ASMI Parallel megafunction provides access to erasable  programmable configurable serial (EPCS) and quad-serial configuration  (EPCQ) devices through parallel data input and output ports."
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
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     value="MAX 10 /// Arria 10 /// Cyclone V /// Arria V GZ /// Arria V /// Stratix V /// Stratix IV /// Cyclone IV GX /// Cyclone IV E /// Cyclone IV GX /// Arria II GZ /// Arria II GX /// Cyclone 10 LP /// Stratix 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altasmi_parallel.pdf" />
 </component>
 <component
   name="altera_asmi_parallel2_top"
   file="pgm/altera_asmi_parallel2_top/altera_asmi_parallel2_top_hw.tcl"
   displayName="ASMI Parallel II IP"
   version="25.1"
   description="The ASMI Parallel megafunction provides access to erasable  programmable configurable serial (EPCS) and quad-serial configuration  (EPCQ) devices through parallel data input and output ports."
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
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     value="MAX 10 /// Arria 10 /// Cyclone V /// Arria V GZ /// Arria V /// Stratix V /// Stratix IV /// Cyclone IV GX /// Cyclone IV E /// Cyclone IV GX /// Arria II GZ /// Arria II GX /// Cyclone 10 LP /// Stratix 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683669/" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683115/" />
 </component>
 <plugin
   name="altera_avalon_cfi_flash_driver"
   file="sopc_builder_ip/altera_avalon_cfi_flash/altera_avalon_cfi_flash_sw.tcl"
   displayName="altera_avalon_cfi_flash_driver"
   version="100.99.98.97"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_cfi_flash"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_avalon_clock_reset_source"
   file="sopc_builder_ip/verification/altera_avalon_clock_reset_source/altera_avalon_clock_reset_source_hw.tcl"
   displayName="Altera Avalon Clock and Reset Source"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_avalon_clock_source"
   file="sopc_builder_ip/verification/altera_avalon_clock_source/altera_avalon_clock_source_hw.tcl"
   displayName="Clock Source BFM Intel FPGA IP"
   version="25.1"
   description="Altera Clock Source BFM"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="none" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471592433" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_avalon_data_pattern_checker"
   file="gx_debug/altera_avalon_data_pattern_checker/altera_avalon_data_pattern_checker_hw.tcl"
   displayName="Altera Avalon Data Pattern Checker"
   version="25.1"
   description="Altera Avalon Data Pattern Checker"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Simulation; Debug and Verification/Verification"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_embedded_ip.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401400496385" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <component
   name="altera_avalon_data_pattern_checker_core"
   file="gx_debug/altera_avalon_data_pattern_checker/altera_avalon_data_pattern_checker_core_hw.tcl"
   displayName="Avalon-ST Data Pattern Checker core"
   version="25.1"
   description="An parallel data pattern checker core"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Verification"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_embedded_ip.pdf" />
 </component>
 <component
   name="altera_avalon_data_pattern_generator"
   file="gx_debug/altera_avalon_data_pattern_generator/altera_avalon_data_pattern_generator_hw.tcl"
   displayName="Altera Avalon Data Pattern Generator"
   version="25.1"
   description="An parallel data pattern generator"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Simulation; Debug and Verification/Verification"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_embedded_ip.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401400496385" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <component
   name="altera_avalon_data_pattern_generator_core"
   file="gx_debug/altera_avalon_data_pattern_generator/altera_avalon_data_pattern_generator_core_hw.tcl"
   displayName="Data Pattern Generator core"
   version="25.1"
   description="An parallel data pattern generator core"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_embedded_ip.pdf" />
 </component>
 <component
   name="altera_avalon_dc_fifo"
   file="sopc_builder_ip/altera_avalon_dc_fifo/altera_avalon_dc_fifo_hw.tcl"
   displayName="Avalon-ST Dual Clock FIFO"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401395563779" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <component
   name="altera_avalon_dma"
   file="sopc_builder_ip/altera_avalon_dma/altera_avalon_dma_hw.tcl"
   displayName="DMA Controller IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/DMA"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401397703359" />
 </component>
 <plugin
   name="altera_avalon_dma_driver"
   file="sopc_builder_ip/altera_avalon_dma/altera_avalon_dma_sw.tcl"
   displayName="altera_avalon_dma_driver"
   version="100.99.98.97"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_dma"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_avalon_em_pc"
   file="alt_mem_if/altera_avalon_mm_efficiency_monitor/top/altera_core_em_pc_hw.tcl"
   displayName="Altera Avalon-MM Efficiency Monitor and Protocol Checker"
   version="25.1"
   description="Altera Avalon-MM Efficiency Monitor and Protocol Checker"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Verification"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="ip_compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_avalon_em_pc_core"
   file="alt_mem_if/altera_avalon_mm_efficiency_monitor/altera_uniphy_efficiency_and_protocol_core/altera_core_em_pc_core_hw.tcl"
   displayName="Altera Avalon-MM Efficiency Monitor and Protcol Checker Core"
   version="25.1"
   description="Altera Avalon-MM Efficiency Monitor and Protocol Checker Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Verification/Internal Components/Performance Monitor Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_avalon_epcs_flash_controller"
   file="sopc_builder_ip/altera_avalon_epcs_flash_controller/altera_avalon_epcs_flash_controller_hw.tcl"
   displayName="Legacy EPCS/EPCQx1 Flash Controller IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Stratix IV /// Stratix V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683130/current/epcs-epcqa-serial-flash-controller-core-57291.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683130/current/epcs-epcqa-serial-flash-controller-core-60270.html" />
 </component>
 <plugin
   name="altera_avalon_epcs_flash_controller_driver"
   file="sopc_builder_ip/altera_avalon_epcs_flash_controller/altera_avalon_epcs_flash_controller_sw.tcl"
   displayName="altera_avalon_epcs_flash_controller_driver"
   version="100.99.98.97"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_epcs_flash_controller"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_avalon_fifo"
   file="sopc_builder_ip/altera_avalon_fifo/altera_avalon_fifo_hw.tcl"
   displayName="Avalon FIFO Memory IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401396003807" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <plugin
   name="altera_avalon_fifo_driver"
   file="sopc_builder_ip/altera_avalon_fifo/altera_avalon_fifo_sw.tcl"
   displayName="altera_avalon_fifo_driver"
   version="100.99.98.97"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_fifo"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_avalon_i2c"
   file="altera_avalon_i2c/altera_avalon_i2c_hw.tcl"
   displayName="Avalon I2C (Master) IP"
   version="25.1"
   description="I2C Core with Avalon MM Slave Interface for configuration"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Serial"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <plugin
   name="altera_avalon_i2c_driver"
   file="altera_avalon_i2c/altera_avalon_i2c_sw.tcl"
   displayName="altera_avalon_i2c_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii,ucosiii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_i2c"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_avalon_interrupt_sink"
   file="sopc_builder_ip/verification/altera_avalon_interrupt_sink/altera_avalon_interrupt_sink_hw.tcl"
   displayName="Avalon Interrupt Sink Intel FPGA IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="none" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471592433" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_avalon_interrupt_source"
   file="sopc_builder_ip/verification/altera_avalon_interrupt_source/altera_avalon_interrupt_source_hw.tcl"
   displayName="Avalon Interrupt Source Intel FPGA IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="none" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471592433" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_avalon_jtag_uart"
   file="sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl"
   displayName="JTAG UART IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Serial"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401317112138" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <plugin
   name="altera_avalon_jtag_uart_driver"
   file="sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_sw.tcl"
   displayName="altera_avalon_jtag_uart_driver"
   version="100.99.98.97"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii,freertos /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_jtag_uart"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="altera_avalon_jtag_uart_lwhal_driver"
   file="sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_lwhal_sw.tcl"
   displayName="altera_avalon_jtag_uart_lwhal_driver"
   version="100.99.98.97"
   description=""
   tags="SW_DRIVER_OS_TYPE=lwhal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_jtag_uart"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="altera_avalon_lan91c111_hal_driver"
   file="sopc_builder_ip/altera_avalon_lan91c111/altera_avalon_lan91c111_hal_sw.tcl"
   displayName="altera_avalon_lan91c111_hal_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_lan91c111"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_avalon_mailbox_simple"
   file="altera_avalon_mailbox/altera_avalon_mailbox_simple_hw.tcl"
   displayName="Avalon Mailbox (simple) IP"
   version="25.1"
   description="This component provides communication channel between two processors in the form of message passing. This component only handle one direction of message passing."
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,interrupt,reset /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Inter-Process Communication"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1431721259859" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <plugin
   name="altera_avalon_mailbox_simple_hal_driver"
   file="altera_avalon_mailbox/altera_avalon_mailbox_simple_sw.tcl"
   displayName="altera_avalon_mailbox_simple_hal_driver"
   version="0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_mailbox_simple"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_avalon_mm_bridge"
   file="merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge_hw.tcl"
   displayName="Avalon-MM Pipeline Bridge"
   version="25.1"
   description="Inserts a register stage in the Avalon-MM command and response paths. Accepts commands on its Avalon-MM slave port and propagates them to its Avalon-MM master port."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset"
   categories="Basic Functions/Bridges and Adaptors/Memory Mapped"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_system_components.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409959275749" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_avalon_mm_cci_bridge"
   file="merlin/altera_avalon_mm_cci_bridge/altera_avalon_mm_cci_bridge_hw.tcl"
   displayName="Avalon-MM to CCI Bridge"
   version="25.1"
   description="This component creates a bridge between an Avalon-MM master and a CCI Standard interface."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset"
   categories="Basic Functions/Bridges and Adaptors/Memory Mapped"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/#update_me_with_actual_link" />
 </component>
 <component
   name="altera_avalon_mm_clock_crossing_bridge"
   file="merlin/altera_avalon_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge_hw.tcl"
   displayName="Avalon-MM Clock Crossing Bridge"
   version="25.1"
   description="Transfers Avalon-MM commands and responses between asynchronous clock domains using asynchronous FIFOs to implement the clock crossing logic."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset"
   categories="Basic Functions/Bridges and Adaptors/Memory Mapped"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
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 <component
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 </component>
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 <component
   name="altera_avalon_monitor_and_gatherer"
   file="sld/trace/monitors/altera_avalon_monitor_and_gatherer/altera_avalon_monitor_and_gatherer_hw.tcl"
   displayName="Throughput Monitor and Stats Gatherer"
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 <component
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   tags="AUTHORSHIP=Altera Corporation"
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 <component
   name="altera_avalon_mutex"
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 <plugin
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   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_mutex"
   categories="driver_element"
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 <plugin
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 <component
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   displayName="On-Chip Memory (RAM or ROM) IP"
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   description=""
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/On Chip Memory"
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 <component
   name="altera_avalon_packets_to_master"
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   displayName="Avalon Packets to Transaction Converter IP"
   version="25.1"
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   tags="AUTHORSHIP=Altera"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
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 </component>
 <component
   name="altera_avalon_performance_counter"
   file="sopc_builder_ip/altera_avalon_performance_counter/altera_avalon_performance_counter_hw.tcl"
   displayName="Performance Counter Unit IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
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   categories="driver_element"
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   description=""
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Peripherals"
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   categories="driver_element"
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   file="sopc_builder_ip/altera_avalon_pixel_converter/altera_avalon_pixel_converter_hw.tcl"
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   description="Altera Avalon-ST Pixel Converter"
   tags="AUTHORSHIP=Intel Corporation"
   categories="Processors and Peripherals/Peripherals"
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 <component
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   description=""
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
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   displayName="Altera Avalon SLD2MM SLD Node"
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   tags="AUTHORSHIP= /// INTERNAL_COMPONENT=true"
   categories=""
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 <component
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   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
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 <plugin
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   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_spi"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
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  <tag2 key="COMPOSITION_CALLBACK" value="composed" />
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     type="OTHER"
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 <component
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 <component
   name="altera_avalon_st_channel_stripper"
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 <component
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   description=""
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 <component
   name="altera_avalon_st_debug_agent_endpoint_bridge"
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   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
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 <component
   name="altera_avalon_st_debug_agent_endpoint_tieoff"
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   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
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 </component>
 <component
   name="altera_avalon_st_debug_host_endpoint"
   file="sld/core/endpoint_wrappers/altera_avalon_st_debug_host_endpoint_hw.tcl"
   displayName="altera_avalon_st_debug_host_endpoint"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_avalon_st_debug_host_endpoint_bridge"
   file="sld/core/endpoint_wrappers/altera_avalon_st_debug_host_endpoint_bridge_hw.tcl"
   displayName="altera_avalon_st_debug_host_endpoint_bridge"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_avalon_st_delay"
   file="avalon_st/altera_avalon_st_delay/altera_avalon_st_delay_hw.tcl"
   displayName="Avalon-ST Delay"
   version="25.1"
   description="Avalon-ST Delay"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401398857652" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_avalon_st_handshake_clock_crosser"
   file="avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser_hw.tcl"
   displayName="Avalon-ST Handshake Clock Crosser"
   version="25.1"
   description="Connects streams that operate at different frequencies using a hand-shaking protocol to propagate transfer control signals and responses across the clock boundary and responses in the other direction."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Bridges and Adapters/Streaming"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="altera_avalon_st_idle_inserter"
   file="sopc_builder_ip/altera_avalon_st_idle_inserter/altera_avalon_st_idle_inserter_hw.tcl"
   displayName="Avalon-ST Idle Inserter"
   version="25.1"
   description="Avalon ST Idle Inserter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Bridges and Adapters/Streaming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_avalon_st_idle_remover"
   file="sopc_builder_ip/altera_avalon_st_idle_remover/altera_avalon_st_idle_remover_hw.tcl"
   displayName="Avalon-ST Idle Remover"
   version="25.1"
   description="Avalon ST Idle Remover"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Bridges and Adapters/Streaming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_avalon_st_monitor"
   file="sopc_builder_ip/verification/altera_avalon_st_monitor_bfm/altera_avalon_st_monitor_hw.tcl"
   displayName="Avalon-ST Monitor Intel FPGA IP"
   version="25.1"
   description="Altera Avalon-ST Monitor"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="none" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,QUARTUS_SYNTH,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471592433" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_avalon_st_null_sink"
   file="sld/trace/core/altera_avalon_st_null_sink/altera_avalon_st_null_sink_hw.tcl"
   displayName="Avalon ST Sink"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_avalon_st_packet_switch"
   file="merlin/altera_avalon_st_packet_switch/altera_avalon_st_packet_switch_hw.tcl"
   displayName="Avalon ST Packet Switch"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="Merlin Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="do_compose" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_avalon_st_packets_to_bytes"
   file="sopc_builder_ip/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes_hw.tcl"
   displayName="Avalon-ST Packets to Bytes Converter IP"
   version="25.1"
   description="Avalon-ST Packets to Bytes Converter"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon_streaming,clock"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="check_maxchannel_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/nios2/qts_qii55012.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401396730179" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <component
   name="altera_avalon_st_pipeline_stage"
   file="avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_hw.tcl"
   displayName="Avalon-ST Pipeline Stage"
   version="25.1"
   description="Inserts a single pipeline (register) stage in the Avalon-ST command and response datapaths. Receives data on its Avalon-ST sink interfaces and drives it unchanged on its Avalon-ST source interface."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409959440867" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_avalon_st_sink_bfm"
   file="sopc_builder_ip/verification/altera_avalon_st_sink_bfm/altera_avalon_st_sink_bfm_hw.tcl"
   displayName="Avalon-ST Sink BFM Intel FPGA IP"
   version="25.1"
   description="Altera Avalon-ST Sink BFM"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="none" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471592433" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_avalon_st_sink_bfm_api_wrapper"
   file="sopc_builder_ip/verification/altera_avalon_st_sink_bfm/altera_avalon_st_sink_bfm_api_wrapper_hw.tcl"
   displayName="Altera Avalon ST Sink BFM with Avalon ST API Wrapper"
   version="25.1"
   description="Altera Avalon ST Sink BFM with Avalon ST API Wrapper"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf" />
 </component>
 <component
   name="altera_avalon_st_source_bfm"
   file="sopc_builder_ip/verification/altera_avalon_st_source_bfm/altera_avalon_st_source_bfm_hw.tcl"
   displayName="Avalon-ST Source BFM Intel FPGA IP"
   version="25.1"
   description="Altera Avalon-ST Source BFM"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="none" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471592433" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_avalon_st_source_bfm_api_wrapper"
   file="sopc_builder_ip/verification/altera_avalon_st_source_bfm/altera_avalon_st_source_bfm_api_wrapper_hw.tcl"
   displayName="Altera Avalon ST Source BFM with Avalon ST API Wrapper"
   version="25.1"
   description="Altera Avalon ST Source BFM with Avalon ST API Wrapper"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf" />
 </component>
 <component
   name="altera_avalon_st_splitter"
   file="avalon_st/altera_avalon_st_splitter/altera_avalon_st_splitter_hw.tcl"
   displayName="Avalon-ST Splitter"
   version="25.1"
   description="Avalon-ST Splitter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401399241593" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <component
   name="altera_avalon_st_tap"
   file="avalon_st/altera_avalon_st_tap/altera_avalon_st_tap_hw.tcl"
   displayName="Avalon-ST Tap"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_avalon_st_tee"
   file="sld/st/altera_avalon_st_tee/altera_avalon_st_tee_hw.tcl"
   displayName="Avalon ST Tee"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <plugin
   name="altera_avalon_sysid_driver"
   file="sopc_builder_ip/altera_avalon_sysid/altera_avalon_sysid_sw.tcl"
   displayName="altera_avalon_sysid_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_sysid"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_avalon_sysid_qsys"
   file="sopc_builder_ip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl"
   displayName="System ID Peripheral IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401400083153" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <plugin
   name="altera_avalon_sysid_qsys_driver"
   file="sopc_builder_ip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_sw.tcl"
   displayName="altera_avalon_sysid_qsys_driver"
   version="100.99.98.97"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_sysid_qsys"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_avalon_throughput_monitor"
   file="sld/trace/monitors/altera_avst_throughput_monitor/altera_avalon_throughput_monitor_hw.tcl"
   displayName="Avalon Throughput Monitor"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="NATIVE_INTERPRETER" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
 </component>
 <component
   name="altera_avalon_timer"
   file="sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl"
   displayName="Interval Timer IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Peripherals"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401398644953" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <plugin
   name="altera_avalon_timer_driver"
   file="sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_sw.tcl"
   displayName="altera_avalon_timer_driver"
   version="100.99.98.97"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_timer"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="altera_avalon_timer_hw.qprs"
   file="sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.qprs"
   displayName="altera_avalon_timer_hw.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_avalon_timer" />
 </plugin>
 <component
   name="altera_avalon_transacto"
   file="sld/mm/altera_avalon_transacto/altera_avalon_transacto_hw.tcl"
   displayName="Altera Avalon Transacto"
   version="25.1"
   description="Altera Avalon Transacto"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Bridges and Adapters/Streaming"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="altera_avalon_uart"
   file="sopc_builder_ip/altera_avalon_uart/altera_avalon_uart_hw.tcl"
   displayName="UART (RS-232 Serial Port) IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Serial"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401317331859" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <plugin
   name="altera_avalon_uart_driver"
   file="sopc_builder_ip/altera_avalon_uart/altera_avalon_uart_sw.tcl"
   displayName="altera_avalon_uart_driver"
   version="100.99.98.97"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii,freertos /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_uart"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="altera_avalon_uart_lwhal_driver"
   file="sopc_builder_ip/altera_avalon_uart/altera_avalon_uart_lwhal_sw.tcl"
   displayName="altera_avalon_uart_lwhal_driver"
   version="100.99.98.97"
   description=""
   tags="SW_DRIVER_OS_TYPE=lwhal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_avalon_uart"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_avalon_video_sync_generator"
   file="sopc_builder_ip/altera_avalon_video_sync_generator/altera_avalon_video_sync_generator_hw.tcl"
   displayName="Video Sync Generator Intel FPGA IP"
   version="25.1"
   description="Altera Video Sync Generator"
   tags="AUTHORSHIP=Intel Corporation"
   categories="Processors and Peripherals/Peripherals"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401398199236" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_avst_throughput_monitor"
   file="sld/trace/monitors/altera_avst_throughput_monitor/altera_avst_throughput_monitor_hw.tcl"
   displayName="AvST Throughput Monitor"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
 </component>
 <component
   name="altera_avst_tmon_mlab"
   file="sld/trace/monitors/altera_avst_tmon_mlab/altera_avst_tmon_mlab_hw.tcl"
   displayName="AvST Throughput Monitor_mlab"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <plugin
   name="altera_axi4_master"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="AXI4 Master"
   version="25.1"
   description="AXI master interfaces are used to issue read and write commands to slave interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="altera_axi4_slave"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="AXI4 Slave"
   version="25.1"
   description="AXI slave interfaces are used to accept and respond to read and write commands issued by master interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="altera_axi4lite_master"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="AXI4Lite Master"
   version="25.1"
   description="AXI 4 Litemaster interfaces are used to issue read and write commands to slave interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="altera_axi4lite_slave"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="AXI4Lite Slave"
   version="25.1"
   description="AXI 4 Lite slave interfaces are used to accept and respond to read and write commands issued by master interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <component
   name="altera_axi_bridge"
   file="merlin/altera_axi_bridge/altera_axi_bridge_hw.tcl"
   displayName="AXI Bridge"
   version="25.1"
   description="AXI/AHB bridge for network topology determination"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Bridges and Adaptors/Memory Mapped"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409959300571" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_axi_default_slave"
   file="merlin/altera_axi_default_slave/altera_axi_default_slave_hw.tcl"
   displayName="AXI Default Slave"
   version="25.1"
   description="AXI Default Slave"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="Documents"
     type="OTHER"
     url="http://www.altera.com/literature/hb/qts/qsys_intro.pdf" />
 </component>
 <plugin
   name="altera_axi_master"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="AXI Master"
   version="25.1"
   description="AXI master interfaces are used to issue read and write commands to slave interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="altera_axi_slave"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="AXI Slave"
   version="25.1"
   description="AXI slave interfaces are used to accept and respond to read and write commands issued by master interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <component
   name="altera_axi_timeout_bridge"
   file="merlin/altera_axi_timeout_bridge/altera_axi_timeout_bridge_hw.tcl"
   displayName="AXI Timeout Bridge"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Bridges and Adaptors/Memory Mapped"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409959313611" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_bch"
   file="dsp/altera_bch/bch_hw.tcl"
   displayName="BCH"
   version="25.1"
   description="Altera BCH"
   tags="AUTHORSHIP=Altera Corporation"
   categories="DSP/Error Detection and Correction"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="do_elaboration" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="EXAMPLE_DESIGN,QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validateTOP_bch" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/dmi1423232706057/dmi1423232847303" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/dmi1436953439900" />
 </component>
 <component
   name="altera_cic_ii"
   file="dsp/altera_cic_ii/altera_cic_ii_hw.tcl"
   displayName="CIC"
   version="25.1"
   description="Altera Cascaded Integrator Comb II"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="DSP/Filters"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix IV /// Stratix V /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// Cyclone IV GX /// Cyclone IV E /// Cyclone V /// Cyclone 10 LP /// MAX 10 /// Stratix 10 for Emulator Use" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_cic_top" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421847945390/hco1421847882821" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697778790" />
 </component>
 <component
   name="altera_clock_bridge"
   file="merlin/altera_clock_bridge/altera_clock_bridge_hw.tcl"
   displayName="Clock Bridge"
   version="25.1"
   description="Allows you to route clocks between Qsys subsystems."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock"
   categories="Basic Functions/Bridges and Adaptors/Clock"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409959266013" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_conduit_bfm"
   file="sopc_builder_ip/verification/altera_conduit_bfm/altera_conduit_bfm_hw.tcl"
   displayName="Conduit BFM Intel FPGA IP"
   version="25.1"
   description="Altera Conduit BFM"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="validate_and_elaborate" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="none" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471592433" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_conduit_pin_divider"
   file="merlin/altera_conduit_pin_divider/altera_conduit_pin_divider_hw.tcl"
   displayName="Conduit Pin Divider"
   version="25.1"
   description="This component converts shared signals into their associated original signals.  Its primary use is for the testbench generator."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit"
   categories="Qsys Interconnect/Tri-State Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_config_slave_endpoint_bridge"
   file="sld/core/endpoint_wrappers/altera_config_slave_endpoint_bridge_hw.tcl"
   displayName="altera_config_slave_endpoint_bridge"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_config_stream_endpoint"
   file="sld/core/endpoint_wrappers/altera_config_stream_endpoint_hw.tcl"
   displayName="altera_config_stream_endpoint"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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   description=""
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 <component
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 <component
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   name="altera_emif_a10_hps"
   file="emif/hwtcl/altera_emif_a10_hps/altera_emif_a10_hps_hw.tcl"
   displayName="External Memory Interfaces for HPS Arria 10 IP"
   version="25.1"
   description="External Memory Interfaces for HPS Arria 10 IP"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Hard Processor Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="COMPOSITION_CALLBACK"
     value="::altera_emif::ip_top::main::composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_emif::ip_top::compat::upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="SUPPRESS_WARNINGS" value="NO_PORTS_AFTER_ELABORATION" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416493470528/hco1416492629263" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697745716" />
  <documentUrl
     displayName="Quick Start"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416493470528/mhi1440164255731" />
 </component>
 <component
   name="altera_emif_arch_nd"
   file="emif/ip_arch_nd/altera_emif_arch_nd_hw.tcl"
   displayName="EMIF Architecture Component for the Stratix 10 Device Family"
   version="25.1"
   description="Altera External Memory Interface Architecture Component for the Stratix 10 Device Family"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_arch_nd::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_arch_nf"
   file="emif/ip_arch_nf/altera_emif_arch_nf_hw.tcl"
   displayName="EMIF Core Component for 20nm Families"
   version="25.1"
   description="Altera External Memory Interface Core Component for 20nm Families"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_arch_nf::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_board_delay_model"
   file="emif/ip_board_delay_model/altera_emif_board_delay_model_hw.tcl"
   displayName="EMIF Example Board Delay Model Component"
   version="25.1"
   description="Altera External Memory Interface Example Board Delay Model Component"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_board_delay_model::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
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     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_cal_slave_nd"
   file="emif/ip_cal_slave/ip_core_nd/altera_emif_cal_slave_nd_hw.tcl"
   displayName="Stratix 10 External Memory Interfaces Calibration Slave/Helper component"
   version="25.1"
   description="This component instantiates components that serve as slaves to the EMIF calibration processor. It is intended for internal use only."
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="COMPOSITION_CALLBACK"
     value="::altera_emif::ip_cal_slave::ip_core_nd::main::composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_cal_slave_nf"
   file="emif/ip_cal_slave/ip_core_nf/altera_emif_cal_slave_nf_hw.tcl"
   displayName="Arria 10 External Memory Interfaces Calibration Slave/Helper component"
   version="25.1"
   description="This component instantiates components that serve as slaves to the EMIF calibration processor. It is intended for internal use only."
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="COMPOSITION_CALLBACK"
     value="::altera_emif::ip_cal_slave::ip_core_nf::main::composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_ctrl_qdr2"
   file="emif/ip_ctrl/ip_qdr2/altera_emif_ctrl_qdr2_hw.tcl"
   displayName="QDRII/II+/II+ Xtreme Soft Memory Controller"
   version="25.1"
   description="Altera External Memory Interface QDRII/II+/II+ Xtreme Soft Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_ctrl::ip_qdr2::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_ctrl_qdr4"
   file="emif/ip_ctrl/ip_qdr4/altera_emif_ctrl_qdr4_hw.tcl"
   displayName="QDR-IV Soft Memory Controller"
   version="25.1"
   description="Altera External Memory Interface QDR-IV Soft Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_ctrl::ip_qdr4::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_ctrl_rld2"
   file="emif/ip_ctrl/ip_rld2/altera_emif_ctrl_rld2_hw.tcl"
   displayName="RLDRAM II Soft Memory Controller"
   version="25.1"
   description="Altera External Memory Interface RLDRAM II Soft Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_ctrl::ip_rld2::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_ctrl_rld3"
   file="emif/ip_ctrl/ip_rld3/altera_emif_ctrl_rld3_hw.tcl"
   displayName="RLDRAM3 Soft Memory Controller"
   version="25.1"
   description="Altera External Memory Interface RLDRAM3 Soft Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_ctrl::ip_rld3::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_ecc"
   file="emif/ip_ecc/ip_top/altera_emif_ecc_hw.tcl"
   displayName="EMIF Error Correction Code (ECC) Component"
   version="25.1"
   description="Altera External Memory Interface Error Correction Code (ECC) Component"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="COMPOSITION_CALLBACK"
     value="::altera_emif::ip_ecc::ip_top::main::composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_ecc_nd"
   file="emif/ip_ecc/ip_core_nd/altera_emif_ecc_nd_hw.tcl"
   displayName="EMIF Error Correction Code (ECC) Component for Stratix 10"
   version="25.1"
   description="Altera External Memory Interface Error Correction Code (ECC) Component for Stratix 10"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_ecc::ip_core_nd::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_ecc_nf"
   file="emif/ip_ecc/ip_core_nf/altera_emif_ecc_nf_hw.tcl"
   displayName="EMIF Error Correction Code (ECC) Component for Arria 10"
   version="25.1"
   description="Altera External Memory Interface Error Correction Code (ECC) Component for Arria 10"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_ecc::ip_core_nf::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_mem_model"
   file="emif/ip_mem_model/ip_top/altera_emif_mem_model_hw.tcl"
   displayName="EMIF Example Memory Model"
   version="25.1"
   description="Altera External Memory Interface Example Memory Model"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="COMPOSITION_CALLBACK"
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_mem_model_core_ddr3"
   file="emif/ip_mem_model/ip_core_ddr3/altera_emif_mem_model_core_ddr3_hw.tcl"
   displayName="EMIF Example DDR3 Memory Model Component"
   version="25.1"
   description="Altera External Memory Interface Example DDR3 Memory Model Component"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_mem_model::ip_core_ddr3::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_mem_model_core_ddr4"
   file="emif/ip_mem_model/ip_core_ddr4/altera_emif_mem_model_core_ddr4_hw.tcl"
   displayName="EMIF Example DDR3 Memory Model Component"
   version="25.1"
   description="Altera External Memory Interface Example DDR3 Memory Model Component"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_mem_model::ip_core_ddr4::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_mem_model_core_lpddr3"
   file="emif/ip_mem_model/ip_core_lpddr3/altera_emif_mem_model_core_lpddr3_hw.tcl"
   displayName="EMIF Example LPDDR3 Memory Model Component"
   version="25.1"
   description="Altera External Memory Interface Example LPDDR3 Memory Model Component"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_mem_model::ip_core_lpddr3::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_mem_model_core_qdr2"
   file="emif/ip_mem_model/ip_core_qdr2/altera_emif_mem_model_core_qdr2_hw.tcl"
   displayName="EMIF Example QDR II/II+/II+ Xtreme Memory Model Component"
   version="25.1"
   description="Altera External Memory Interface Example II/II+/II+ Xtreme Memory Model Component"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_mem_model::ip_core_qdr2::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_mem_model_core_qdr4"
   file="emif/ip_mem_model/ip_core_qdr4/altera_emif_mem_model_core_qdr4_hw.tcl"
   displayName="EMIF Example QDR-IV Memory Model Component"
   version="25.1"
   description="Altera External Memory Interface Example QDR-IV Memory Model Component"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_mem_model::ip_core_qdr4::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_mem_model_core_rld2"
   file="emif/ip_mem_model/ip_core_rld2/altera_emif_mem_model_core_rld2_hw.tcl"
   displayName="EMIF Example RLD2 Memory Model Component"
   version="25.1"
   description="Altera External Memory Interface Example RLD2 Memory Model Component"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_mem_model::ip_core_rld2::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_mem_model_core_rld3"
   file="emif/ip_mem_model/ip_core_rld3/altera_emif_mem_model_core_rld3_hw.tcl"
   displayName="EMIF Example RLD3 Memory Model Component"
   version="25.1"
   description="Altera External Memory Interface Example RLD3 Memory Model Component"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_mem_model::ip_core_rld3::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_s10"
   file="emif/hwtcl/altera_emif_s10/altera_emif_s10_hw.tcl"
   displayName="Stratix 10 External Memory Interfaces"
   version="25.1"
   description="Stratix 10 External Memory Interfaces"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Memory Interfaces and Controllers"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="COMPOSITION_CALLBACK"
     value="::altera_emif::ip_top::main::composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_emif::ip_top::compat::upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="SUPPRESS_WARNINGS" value="NO_PORTS_AFTER_ELABORATION" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/products/fpga/stratix-series/stratix-10/features.html#externalmemoryinterfaces" />
 </component>
 <component
   name="altera_emif_s10_hps"
   file="emif/hwtcl/altera_emif_s10_hps/altera_emif_s10_hps_hw.tcl"
   displayName="Stratix 10 External Memory Interfaces for HPS"
   version="25.1"
   description="Stratix 10 External Memory Interfaces for HPS"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Hard Processor Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="COMPOSITION_CALLBACK"
     value="::altera_emif::ip_top::main::composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_emif::ip_top::compat::upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="SUPPRESS_WARNINGS" value="NO_PORTS_AFTER_ELABORATION" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/products/fpga/stratix-series/stratix-10/features.html#externalmemoryinterfaces" />
 </component>
 <component
   name="altera_emif_sig_splitter"
   file="emif/ip_sig_splitter/altera_emif_sig_splitter_hw.tcl"
   displayName="Signal Splitter for EMIF Example Design"
   version="25.1"
   description="Altera External Memory Interface Signal Splitter for Example Design"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_sig_splitter::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_sim_checker"
   file="emif/ip_sim_checker/altera_emif_sim_checker_hw.tcl"
   displayName="Simulation Checker for EMIF Example Traffic Generator"
   version="25.1"
   description="Altera External Memory Interface Simulation Checker for Example Avalon Traffic Generator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_sim_checker::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_soft_nios"
   file="emif/ip_soft_nios/altera_emif_soft_nios_hw.tcl"
   displayName="Arria 10 External Memory Interfaces Calibration Debug Component"
   version="25.1"
   description="This component must be connected to one of the EMIF cores in an I/O column in order to debug EMIF calibration code. It is intended for internal use only."
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="COMPOSITION_CALLBACK"
     value="::altera_emif::ip_soft_nios::main::composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_tg_afi_ddr3"
   file="emif/ip_tg_afi/ip_ddr3/altera_emif_tg_afi_ddr3_hw.tcl"
   displayName="Example DDR3 AFI Traffic Generator"
   version="25.1"
   description="Altera External Memory Interface Example DDR3 AFI Traffic Generator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_tg_afi::ip_ddr3::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_tg_afi_ddr4"
   file="emif/ip_tg_afi/ip_ddr4/altera_emif_tg_afi_ddr4_hw.tcl"
   displayName="Example DDR4 AFI Traffic Generator"
   version="25.1"
   description="Altera External Memory Interface Example DDR4 AFI Traffic Generator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_tg_afi::ip_ddr4::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_tg_afi_lpddr3"
   file="emif/ip_tg_afi/ip_lpddr3/altera_emif_tg_afi_lpddr3_hw.tcl"
   displayName="Example LPDDR3 AFI Traffic Generator"
   version="25.1"
   description="Altera External Memory Interface Example LPDDR3 AFI Traffic Generator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_tg_afi::ip_lpddr3::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_tg_afi_qdr4"
   file="emif/ip_tg_afi/ip_qdr4/altera_emif_tg_afi_qdr4_hw.tcl"
   displayName="Example QDR-IV AFI Traffic Generator"
   version="25.1"
   description="Altera External Memory Interface Example QDR-IV AFI Traffic Generator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_tg_afi::ip_qdr4::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_tg_afi_rld3"
   file="emif/ip_tg_afi/ip_rld3/altera_emif_tg_afi_rld3_hw.tcl"
   displayName="Example RLDRAM3 AFI Traffic Generator"
   version="25.1"
   description="Altera External Memory Interface Example RLDRAM3 AFI Traffic Generator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_tg_afi::ip_rld3::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_tg_avl"
   file="emif/ip_tg_avl/altera_emif_tg_avl_hw.tcl"
   displayName="EMIF Example Avalon Traffic Generator"
   version="25.1"
   description="Altera External Memory Interface Example Avalon Traffic Generator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_tg_avl::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emif_tg_avl_2"
   file="emif/ip_tg_avl_2/altera_emif_tg_avl_2_hw.tcl"
   displayName="EMIF Example Configurable Avalon Traffic Generator"
   version="25.1"
   description="Altera External Memory Interface Example Configurable Avalon Traffic Generator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Internal Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_emif::ip_tg_avl_2::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="altera_emr_unloader"
   file="altera_emr_unloader/altera_emr_unloader/altera_emr_unloader_hw.tcl"
   displayName="Altera Error Message Register Unloader"
   version="25.1"
   description="Altera Error Message Register Unloader provides parallel interface for EMR."
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix IV /// Arria II GZ /// Arria II GX /// Stratix V /// Arria V /// Arria V GZ /// Cyclone V /// Arria 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_emr_unloader.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/esc1417461530107/esc1417477325834" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_emr_unloader2"
   file="pgm/altera_emr_unloader/altera_emr_unloader2/altera_emr_unloader_hw.tcl"
   displayName="Error Message Register Unloader IP"
   version="25.1"
   description="Error Message Register Unloader provides parallel interface for EMR."
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix IV /// Arria II GZ /// Arria II GX /// Stratix V /// Arria V /// Arria V GZ /// Cyclone V /// Arria 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/esc1417461530107.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/jna1517813430195.html" />
 </component>
 <component
   name="altera_emr_unloader_core"
   file="altera_emr_unloader/altera_emr_unloader_core/emr_unloader_core_hw.tcl"
   displayName="Altera EMR Unloader Core"
   version="25.1"
   description="Altera EMR Unloader core component"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Configuration &amp; Programming"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix IV /// Arria II GZ /// Arria II GX /// Stratix V /// Arria V /// Arria V GZ /// Cyclone V /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_emr_unloader.pdf" />
 </component>
 <component
   name="altera_emr_unloader_core2"
   file="pgm/altera_emr_unloader/altera_emr_unloader_core2/emr_unloader_core_hw.tcl"
   displayName="EMR Unloader Core"
   version="25.1"
   description="EMR Unloader core component"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Configuration &amp; Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix IV /// Arria II GZ /// Arria II GX /// Stratix V /// Arria V /// Arria V GZ /// Cyclone V /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_emr_unloader.pdf" />
 </component>
 <component
   name="altera_epcq_controller"
   file="altera_epcq_controller/altera_epcq_controller_wrapper_hw.tcl"
   displayName="Serial Flash Controller IP"
   version="25.1"
   description="This component is a serial flash controller which allows user to access Altera FPGA EPCQ devices"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,interrupt,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Cyclone V /// Arria V GZ /// Arria V /// Stratix V /// Stratix IV /// Cyclone IV GX /// Cyclone IV E /// Cyclone IV GX /// Arria II GZ /// Arria II GX /// Cyclone 10 LP" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1431459459085" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <component
   name="altera_epcq_controller2"
   file="pgm/altera_epcq_controller2/altera_epcq_controller2_hw.tcl"
   displayName="Serial Flash Controller II IP"
   version="25.1"
   description="This component is a serial flash controller which allows user to access Altera EPCQ devices"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Cyclone V /// Arria V GZ /// Arria V /// Stratix V /// Stratix IV /// Cyclone IV GX /// Cyclone IV E /// Cyclone IV GX /// Arria II GZ /// Arria II GX /// Cyclone 10 LP" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html#eym1535045655173" />
 </component>
 <plugin
   name="altera_epcq_controller2_driver"
   file="pgm/altera_epcq_controller2/altera_epcq_controller2_sw.tcl"
   displayName="altera_epcq_controller2_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_epcq_controller2"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_epcq_controller_core"
   file="altera_epcq_controller/altera_epcq_controller_hw.tcl"
   displayName="EPCQ Serial Flash controller core IP"
   version="25.1"
   description="This component is a serial flash controller which allows user to access Altera FPGA EPCQ devices"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <plugin
   name="altera_epcq_controller_driver"
   file="altera_epcq_controller/altera_epcq_controller_sw.tcl"
   displayName="altera_epcq_controller_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_epcq_controller"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_error_response_slave"
   file="merlin/altera_error_response_slave/altera_error_response_slave_hw.tcl"
   displayName="Error Response Slave"
   version="25.1"
   description="Error Response Slave"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="Documents"
     type="OTHER"
     url="http:/www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_eth_10g_design_example"
   file="ethernet/altera_eth_10g_design_example/source/altera_eth_10g_design_example_hw.tcl"
   displayName="Altera Ethernet 10G Design Example"
   version="25.1"
   description="Altera Ethernet 10G Design Example"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Reference Designs/Reference Design Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/10Gbps_MAC.pdf" />
 </component>
 <component
   name="altera_eth_10g_mac"
   file="ethernet/altera_eth_10g_mac/altera_eth_10g_mac_hw.tcl"
   displayName="Ethernet 10G MAC IP"
   version="25.1"
   description="Ethernet 10G MAC IP"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Ethernet/10G to 1G Multi-rate Ethernet"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria II GX /// Arria II GZ /// Cyclone IV GX /// Stratix IV /// Stratix V /// Arria V /// Cyclone V /// Arria V GZ" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/10Gbps_MAC.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/10gbps_mac.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/altera-www/global/en_us/index/documentation/hco1421697699431.html" />
 </component>
 <component
   name="altera_eth_10g_mac_base_r"
   file="ethernet/altera_eth_10g_design_example/altera_eth_10g_mac_base_r/altera_eth_10g_mac_base_r.qsys"
   displayName="altera_eth_10g_mac_base_r"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_10g_mac_base_r_1588"
   file="ethernet/altera_eth_10g_design_example/altera_eth_10g_mac_base_r_1588/altera_eth_10g_mac_base_r_1588.qsys"
   displayName="altera_eth_10g_mac_base_r_1588"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_10g_mac_base_r_sv"
   file="ethernet/altera_eth_10g_design_example/altera_eth_10g_mac_base_r_sv/altera_eth_10g_mac_base_r_sv.qsys"
   displayName="altera_eth_10g_mac_base_r_sv"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_10g_mac_xaui"
   file="ethernet/altera_eth_10g_design_example/altera_eth_10g_mac_xaui/altera_eth_10g_mac_xaui.qsys"
   displayName="altera_eth_10g_mac_xaui"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_10g_mac_xaui_sv"
   file="ethernet/altera_eth_10g_design_example/altera_eth_10g_mac_xaui_sv/altera_eth_10g_mac_xaui_sv.qsys"
   displayName="altera_eth_10g_mac_xaui_sv"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_10g_rx_register_map"
   file="ethernet/ethernet_ucore/altera_eth_10g_rx_register_map/altera_eth_10g_rx_register_map_hw.tcl"
   displayName="Ethernet 10G MAC RX Register Map"
   version="25.1"
   description="Altera Ethernet 10G MAC RX Register Map"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_10g_tx_register_map"
   file="ethernet/ethernet_ucore/altera_eth_10g_tx_register_map/altera_eth_10g_tx_register_map_hw.tcl"
   displayName="Ethernet 10G MAC TX Register Map"
   version="25.1"
   description="Altera Ethernet 10G MAC TX Register Map"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_10gbaser_phy_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER/rtl/phy/altera_eth_10gbaser_phy_a10.qsys"
   displayName="altera_eth_10gbaser_phy_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_10gkr_phy_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE/rtl/phy/altera_eth_10gkr_phy_a10.qsys"
   displayName="altera_eth_10gkr_phy_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_10gkr_phy_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/phy/altera_eth_10gkr_phy_a10.qsys"
   displayName="altera_eth_10gkr_phy_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_10gkr_phy_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE/rtl/phy/altera_eth_10gkr_phy_a10.qsys"
   displayName="altera_eth_10gkr_phy_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_10gkr_phy_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/phy/altera_eth_10gkr_phy_a10.qsys"
   displayName="altera_eth_10gkr_phy_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_10gmem_statistics_collector"
   file="ethernet/ethernet_ucore/altera_eth_10gmem_statistics_collector/altera_eth_10gmem_statistics_collector_hw.tcl"
   displayName="Ethernet 10G Statistics Collector in Memory"
   version="25.1"
   description="Altera Ethernet 10G Statistics Collector using Memory"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_1588_tod"
   file="ethernet/ethernet_ucore/altera_eth_1588_tod/altera_eth_1588_tod_hw.tcl"
   displayName="Ethernet IEEE 1588 Time of Day Clock IP"
   version="25.1"
   description="Provides a stream of timestamps for use timestamping IEEE 1588 packets and other events."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Ethernet/Reference Design Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="MAX 10 /// Arria 10 /// Stratix V /// Arria V /// Arria V GZ /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683044/current/time-of-day-clock.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683598/" />
 </component>
 <component
   name="altera_eth_1588_tod_10g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod/altera_eth_1588_tod_10g_a10.qsys"
   displayName="altera_eth_1588_tod_10g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_10g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod/altera_eth_1588_tod_10g_a10.qsys"
   displayName="altera_eth_1588_tod_10g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_1g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod/altera_eth_1588_tod_1g_a10.qsys"
   displayName="altera_eth_1588_tod_1g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_1g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod/altera_eth_1588_tod_1g_a10.qsys"
   displayName="altera_eth_1588_tod_1g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_master_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod/altera_eth_1588_tod_master_a10.qsys"
   displayName="altera_eth_1588_tod_master_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_master_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod/altera_eth_1588_tod_master_a10.qsys"
   displayName="altera_eth_1588_tod_master_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_sync_64b_10g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod_sync/altera_eth_1588_tod_sync_64b_10g_a10.qsys"
   displayName="altera_eth_1588_tod_sync_64b_10g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_sync_64b_10g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod_sync/altera_eth_1588_tod_sync_64b_10g_a10.qsys"
   displayName="altera_eth_1588_tod_sync_64b_10g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_sync_64b_1g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod_sync/altera_eth_1588_tod_sync_64b_1g_a10.qsys"
   displayName="altera_eth_1588_tod_sync_64b_1g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_sync_64b_1g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod_sync/altera_eth_1588_tod_sync_64b_1g_a10.qsys"
   displayName="altera_eth_1588_tod_sync_64b_1g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_sync_96b_10g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod_sync/altera_eth_1588_tod_sync_96b_10g_a10.qsys"
   displayName="altera_eth_1588_tod_sync_96b_10g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_sync_96b_10g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod_sync/altera_eth_1588_tod_sync_96b_10g_a10.qsys"
   displayName="altera_eth_1588_tod_sync_96b_10g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_sync_96b_1g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod_sync/altera_eth_1588_tod_sync_96b_1g_a10.qsys"
   displayName="altera_eth_1588_tod_sync_96b_1g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_sync_96b_1g_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/altera_eth_1588_tod_sync/altera_eth_1588_tod_sync_96b_1g_a10.qsys"
   displayName="altera_eth_1588_tod_sync_96b_1g_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_eth_1588_tod_synchronizer"
   file="ethernet/ethernet_ucore/altera_eth_1588_tod_synchronizer/altera_eth_1588_tod_synchronizer_hw.tcl"
   displayName="Ethernet IEEE 1588 TOD Synchronizer IP"
   version="25.1"
   description="Provide synchronization between 2 TOD with different phase or ppm or freq, eg 1G and 10G."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Ethernet/Reference Design Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Stratix V /// Arria V /// Arria V GZ /// Cyclone V /// MAX 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683044/current/time-of-day-synchronizer.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683598/" />
 </component>
 <component
   name="altera_eth_2_5g_mac"
   file="ethernet/altera_eth_2_5g_mac/altera_eth_2_5g_mac_hw.tcl"
   displayName="Ethernet 2.5G MAC Intel FPGA IP"
   version="25.1"
   description="Ethernet 2.5G MAC"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_2_5g_pcs_16b"
   file="ethernet/altera_eth_2_5g_pcs_pma_16b/altera_eth_2_5g_pcs_16b_hw.tcl"
   displayName="Ethernet 2.5G PCS Intel FPGA IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_2_5g_pcs_pma_16b"
   file="ethernet/altera_eth_2_5g_pcs_pma_16b/altera_eth_2_5g_pcs_pma_16b_hw.tcl"
   displayName="Ethernet 2.5G PHY Intel FPGA IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
 </component>
 <component
   name="altera_eth_2_5g_system"
   file="ethernet/altera_eth_2_5g_system/altera_eth_2_5g_system_hw.tcl"
   displayName="Ethernet 2.5Gb Intel FPGA Design Example"
   version="25.1"
   description="Ethernet 2.5Gb System"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Stratix V /// Stratix IV /// Arria II GX /// Arria V /// Arria V GZ /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_address_inserter"
   file="ethernet/ethernet_ucore/altera_eth_address_inserter/altera_eth_address_inserter_hw.tcl"
   displayName="Ethernet Source Address Inserter"
   version="25.1"
   description="Altera Ethernet Source Address Inserter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_avst2gmii_converter"
   file="ethernet/ethernet_ucore/altera_eth_avst2gmii_converter/altera_eth_avst2gmii_converter_hw.tcl"
   displayName="Ethernet Avalon-ST to GMII Converter"
   version="25.1"
   description="Altera Ethernet Avalon-ST to GMII Converter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_eth_channel_adapter"
   file="ethernet/ethernet_ucore/altera_eth_adapters/altera_eth_channel_adapter/altera_eth_channel_adapter_hw.tcl"
   displayName="Ethernet XGMII Channel Adapter"
   version="25.1"
   description="Ethernet XGMII Channel Adapter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
 </component>
 <component
   name="altera_eth_crc"
   file="ethernet/ethernet_ucore/altera_eth_crc/altera_eth_crc_hw.tcl"
   displayName="Ethernet CRC"
   version="25.1"
   description="Altera Ethernet CRC"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_eth_crc_allocation"
   file="ethernet/ethernet_ucore/altera_eth_crc_allocation/altera_eth_crc_allocation_hw.tcl"
   displayName="Ethernet CRC Allocation"
   version="25.1"
   description="Altera Ethernet CRC Allocation"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_crc_pad_rem"
   file="ethernet/ethernet_ucore/altera_eth_crc_pad_rem/altera_eth_crc_pad_rem_hw.tcl"
   displayName="Ethernet CRC PAD Remover"
   version="25.1"
   description="Ethernet CRC PAD Remover"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_databus_bit_inserter"
   file="ethernet/ethernet_ucore/altera_eth_databus_bit_inserter/altera_eth_databus_bit_inserter_hw.tcl"
   displayName="altera_eth_databus_bit_inserter"
   version="25.1"
   description="altera_eth_databus_bit_inserter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_eth_default_slave"
   file="ethernet/ethernet_ucore/altera_eth_default_slave/altera_eth_default_slave_hw.tcl"
   displayName="Ethernet Default Slave"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_fifo_pause_ctrl_adapter"
   file="ethernet/altera_eth_10g_design_example/design_example_components/altera_eth_fifo_pause_ctrl_adapter/altera_eth_fifo_pause_ctrl_adapter_hw.tcl"
   displayName="Ethernet FIFO Pause Control Adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Reference Designs/Reference Design Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
 </component>
 <component
   name="altera_eth_frame_decoder"
   file="ethernet/ethernet_ucore/altera_eth_frame_decoder/altera_eth_frame_decoder_hw.tcl"
   displayName="Ethernet Frame Decoder"
   version="25.1"
   description="Altera Ethernet Frame Decoder"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_frame_decoder_2_5g"
   file="ethernet/ethernet_ucore/altera_eth_frame_decoder_2_5g/altera_eth_frame_decoder_2_5g_hw.tcl"
   displayName="Ethernet Frame Decoder"
   version="25.1"
   description="Altera Ethernet Frame Decoder 2.5G"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_frame_status_merger"
   file="ethernet/ethernet_ucore/altera_eth_frame_status_merger/altera_eth_frame_status_merger_hw.tcl"
   displayName="Ethernet Frame Status Merger"
   version="25.1"
   description="Altera Ethernet Frame Status Merger"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_gmii2avst_converter"
   file="ethernet/ethernet_ucore/altera_eth_gmii2avst_converter/altera_eth_gmii2avst_converter_hw.tcl"
   displayName="Ethernet GMII to Avalon-ST Converter"
   version="25.1"
   description="Altera Ethernet GMII to Avalon-ST Converter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_eth_gmii_crc"
   file="ethernet/ethernet_ucore/altera_eth_gmii_crc/altera_eth_gmii_crc_hw.tcl"
   displayName="Ethernet GMII CRC"
   version="25.1"
   description="Altera Ethernet GMII CRC"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_gmii_mii_decoder"
   file="ethernet/ethernet_ucore/altera_eth_gmii_mii_decoder/altera_eth_gmii_mii_decoder_hw.tcl"
   displayName="altera_eth_gmii_mii_decoder"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_gmii_mii_encoder"
   file="ethernet/ethernet_ucore/altera_eth_gmii_mii_encoder/altera_eth_gmii_mii_encoder_hw.tcl"
   displayName="altera_eth_gmii_mii_encoder"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_gmii_ptp_inserter"
   file="ethernet/ethernet_ucore/altera_eth_gmii_ptp_inserter/altera_eth_gmii_ptp_inserter_hw.tcl"
   displayName="Ethernet GMII PTP Inserter"
   version="25.1"
   description="Altera Ethernet GMII PTP Inserter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_gmii_tsu"
   file="ethernet/ethernet_ucore/altera_eth_gmii_tsu/altera_eth_gmii_tsu_hw.tcl"
   displayName="Ethernet GMII TSU"
   version="25.1"
   description="Altera Ethernet GMII TSU"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_eth_interface_conversion"
   file="ethernet/ethernet_ucore/altera_eth_adapters/altera_eth_interface_conversion/altera_eth_interface_conversion_hw.tcl"
   displayName="Ethernet XGMII Interface Conversion"
   version="25.1"
   description="Ethernet XGMII Interface Conversion"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
 </component>
 <component
   name="altera_eth_lane_decoder"
   file="ethernet/ethernet_ucore/altera_eth_lane_decoder/altera_eth_lane_decoder_hw.tcl"
   displayName="Ethernet Lane Decoder"
   version="25.1"
   description="Altera Eth Lane Decoder"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_lane_decoder_2_5g"
   file="ethernet/ethernet_ucore/altera_eth_lane_decoder_2_5g/altera_eth_lane_decoder_2_5g_hw.tcl"
   displayName="altera_eth_lane_decoder_2_5g"
   version="25.1"
   description="altera_eth_lane_decoder_2_5g"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
 </component>
 <component
   name="altera_eth_lane_encoder_2_5g"
   file="ethernet/ethernet_ucore/altera_eth_lane_encoder_2_5g/altera_eth_lane_encoder_2_5g_hw.tcl"
   displayName="altera_eth_lane_encoder_2_5g"
   version="25.1"
   description="altera_eth_lane_encoder_2_5g"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
 </component>
 <component
   name="altera_eth_link_fault_detection"
   file="ethernet/ethernet_ucore/altera_eth_link_fault_detection/altera_eth_link_fault_detection_hw.tcl"
   displayName="Ethernet Link Fault Detection"
   version="25.1"
   description="Altera Ethernet Link Fault Detection"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
 </component>
 <component
   name="altera_eth_link_fault_generation"
   file="ethernet/ethernet_ucore/altera_eth_link_fault_generation/altera_eth_link_fault_generation_hw.tcl"
   displayName="Ethernet Link Fault Generation"
   version="25.1"
   description="Altera Ethernet Link Fault Generation"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
 </component>
 <component
   name="altera_eth_link_fault_generation_unidirectional"
   file="ethernet/ethernet_ucore/altera_eth_link_fault_generation_unidirectional/altera_eth_link_fault_generation_unidirectional_hw.tcl"
   displayName="Ethernet Link Fault Generation with Unidirectional Transport"
   version="25.1"
   description="Altera Ethernet Link Fault Generation with Unidirectional Transport"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
 </component>
 <component
   name="altera_eth_loopback"
   file="ethernet/altera_eth_10g_design_example/design_example_components/altera_eth_loopback/altera_eth_loopback_hw.tcl"
   displayName="Ethernet Loopback"
   version="25.1"
   description="Altera Ethernet Loopback"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Reference Designs/Reference Design Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_eth_loopback_composed"
   file="ethernet/altera_eth_10g_design_example/design_example_components/altera_eth_loopback_composed/altera_eth_loopback_composed_hw.tcl"
   displayName="Ethernet Loopback Composed"
   version="25.1"
   description="Altera Ethernet Loopback Composed"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Reference Designs/Reference Design Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_mdio"
   file="ethernet/ethernet_ucore/altera_eth_mdio/altera_eth_mdio_hw.tcl"
   displayName="Ethernet MDIO IP"
   version="25.1"
   description="Ethernet MDIO Intel FPGA IP"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Ethernet/Reference Design Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// MAX 10 /// Stratix V /// Stratix IV /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Cyclone V /// Cyclone IV E /// Cyclone IV GX" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html#iga1401395383139" />
 </component>
 <component
   name="altera_eth_packet_classifier"
   file="ethernet/altera_eth_10g_design_example/design_example_components/altera_eth_packet_classifier/altera_eth_packet_classifier_hw.tcl"
   displayName="Ethernet Packet Classifier IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Ethernet/Reference Design Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="MAX 10 /// Arria 10 /// Stratix V /// Arria V /// Arria V GZ /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20019.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/nfa1453869442912.html#nfa1453883305293" />
 </component>
 <component
   name="altera_eth_packet_formatter"
   file="ethernet/ethernet_ucore/altera_eth_packet_formatter/altera_eth_packet_formatter_hw.tcl"
   displayName="Ethernet Packet Formatter"
   version="25.1"
   description="Altera Ethernet Packet Formatter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_packet_overflow_control"
   file="ethernet/ethernet_ucore/altera_eth_packet_overflow_control/altera_eth_packet_overflow_control_hw.tcl"
   displayName="Ethernet Packet Overflow Control"
   version="25.1"
   description="Packet Ethernet Packet Overflow Control"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_packet_underflow_control"
   file="ethernet/ethernet_ucore/altera_eth_packet_underflow_control/altera_eth_packet_underflow_control_hw.tcl"
   displayName="Ethernet Packet Underflow Control"
   version="25.1"
   description="Altera Ethernet Packet Underflow Control"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
 </component>
 <component
   name="altera_eth_pad_inserter"
   file="ethernet/ethernet_ucore/altera_eth_pad_inserter/altera_eth_pad_inserter_hw.tcl"
   displayName="Ethernet Pad Inserter"
   version="25.1"
   description="Altera Ethernet Pad Inserter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_pause_beat_conversion"
   file="ethernet/ethernet_ucore/altera_eth_pause_beat_conversion/altera_eth_pause_beat_conversion_hw.tcl"
   displayName="Ethernet Pause Beat Conversion"
   version="25.1"
   description="Altera Ethernet Pause Beat Conversion"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_pause_ctrl_gen"
   file="ethernet/ethernet_ucore/altera_eth_pause_controller_and_generator/altera_eth_pause_ctrl_gen_hw.tcl"
   displayName="Ethernet Pause Controller and Generator"
   version="25.1"
   description="Altera Ethernet Pause Controller and Generator"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
 </component>
 <component
   name="altera_eth_pause_req_termination"
   file="ethernet/ethernet_ucore/altera_eth_adapters/altera_eth_pause_req_termination/altera_eth_pause_req_termination_hw.tcl"
   displayName="Ethernet Pause Request Termination"
   version="25.1"
   description="Ethernet Pause Request Termination"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
 </component>
 <component
   name="altera_eth_pfc_generator"
   file="ethernet/ethernet_ucore/altera_eth_pfc_generator/altera_eth_pfc_generator_hw.tcl"
   displayName="Ethernet PFC Generator"
   version="25.1"
   description="Altera Ethernet PFC Generator"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
 </component>
 <component
   name="altera_eth_pfc_pause_conversion"
   file="ethernet/ethernet_ucore/altera_eth_pfc_pause_conversion/altera_eth_pfc_pause_conversion_hw.tcl"
   displayName="Ethernet PFC Pause Conversion"
   version="25.1"
   description="Altera Ethernet PFC Pause Conversion"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_pkt_backpressure_control"
   file="ethernet/ethernet_ucore/altera_eth_pkt_backpressure_control/altera_eth_pkt_backpressure_control_hw.tcl"
   displayName="Ethernet Packet Backpressure Controller"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_preamble_custom"
   file="ethernet/ethernet_ucore/altera_eth_preamble_custom/altera_eth_preamble_custom_hw.tcl"
   displayName="altera_eth_preamble_custom"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="altera_eth_preamble_inserter"
   file="ethernet/ethernet_ucore/altera_eth_preamble_inserter/altera_eth_preamble_inserter_hw.tcl"
   displayName="Preamble Inserter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_eth_rs_demux"
   file="ethernet/ethernet_ucore/altera_eth_adapters/altera_eth_rs_demux/altera_eth_rs_demux_hw.tcl"
   displayName="altera_eth_rs_demux"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_rs_mux"
   file="ethernet/ethernet_ucore/altera_eth_adapters/altera_eth_rs_mux/altera_eth_rs_mux_hw.tcl"
   displayName="altera_eth_rs_mux"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_eth_splitter"
   file="ethernet/ethernet_ucore/altera_eth_adapters/altera_eth_splitter/altera_eth_splitter_hw.tcl"
   displayName="altera_eth_splitter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_statistics_collector"
   file="ethernet/ethernet_ucore/altera_eth_statistics_collector/altera_eth_statistics_collector_hw.tcl"
   displayName="Ethernet Statistics Collector"
   version="25.1"
   description="Altera Ethernet Statistics Collector"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_timestamp_aligner"
   file="ethernet/ethernet_ucore/altera_eth_timestamp_aligner/altera_eth_timestamp_aligner_hw.tcl"
   displayName="Ethernet Timestamp Aligner"
   version="25.1"
   description="Altera Ethernet TIMESTAMP ALIGNER"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_eth_timestamp_req_ctrl"
   file="ethernet/ethernet_ucore/altera_eth_timestamp_req_ctrl/altera_eth_timestamp_req_ctrl_hw.tcl"
   displayName="Ethernet Timestamp Request Control"
   version="25.1"
   description="Altera Ethernet Timestamp Request Control"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_tse"
   file="ethernet/altera_eth_tse/altera_eth_tse_hw.tcl"
   displayName="Triple-Speed Ethernet IP"
   version="25.1"
   description="Triple Speed Ethernet IP"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Ethernet/1G Multi-rate Ethernet"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="MAX 10 /// Arria 10 /// Stratix V /// Stratix IV /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Cyclone V /// Cyclone IV E /// Cyclone IV GX /// Cyclone 10 LP" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_ethernet.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/bhc1410932355850.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/hco1421697984525.html" />
 </component>
 <component
   name="altera_eth_tse_altgxb"
   file="ethernet/tse_ucores/altera_eth_tse_altgxb/altera_eth_tse_altgxb_hw.tcl"
   displayName="altera_eth_tse_altgxb"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_tse_avalon_arbiter"
   file="ethernet/tse_ucores/altera_eth_tse_avalon_arbiter/altera_eth_tse_avalon_arbiter_hw.tcl"
   displayName="altera_eth_tse_avalon_arbiter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_bridge"
   file="ethernet/tse_ucores/altera_eth_tse_bridge/altera_eth_tse_bridge_hw.tcl"
   displayName="altera_eth_tse_bridge"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_channel_adapter"
   file="ethernet/tse_ucores/altera_eth_tse_channel_adapter/altera_eth_tse_channel_adapter_hw.tcl"
   displayName="altera_eth_tse_channel_adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_conduit_fanout"
   file="ethernet/tse_ucores/altera_eth_tse_conduit_fanout/altera_eth_tse_conduit_fanout_hw.tcl"
   displayName="altera_eth_tse_conduit_fanout"
   version="25.1"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <plugin
   name="altera_eth_tse_driver_hal"
   file="ethernet/altera_eth_tse/src/software/lib/altera_eth_tse_hal_sw.tcl"
   displayName="altera_eth_tse_driver_hal"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_eth_tse"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_eth_tse_fifoless_mac"
   file="ethernet/tse_ucores/altera_eth_tse_fifoless_mac/altera_eth_tse_fifoless_mac_hw.tcl"
   displayName="altera_eth_tse_fifoless_mac"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_mac"
   file="ethernet/tse_ucores/altera_eth_tse_mac/altera_eth_tse_mac_hw.tcl"
   displayName="altera_eth_tse_mac"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_nf_lvds_terminator"
   file="ethernet/tse_ucores/altera_eth_tse_nf_lvds_terminator/altera_eth_tse_nf_lvds_terminator_hw.tcl"
   displayName="altera_eth_tse_nf_lvds_terminator"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_nf_phyip_terminator"
   file="ethernet/tse_ucores/altera_eth_tse_nf_phyip_terminator/altera_eth_tse_nf_phyip_terminator_hw.tcl"
   displayName="altera_eth_tse_nf_phyip_terminator"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_pcs"
   file="ethernet/tse_ucores/altera_eth_tse_pcs/altera_eth_tse_pcs_hw.tcl"
   displayName="altera_eth_tse_pcs"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_pcs_pma_gxb"
   file="ethernet/tse_ucores/altera_eth_tse_pcs_pma_gxb/altera_eth_tse_pcs_pma_gxb_hw.tcl"
   displayName="altera_eth_tse_pcs_pma_gxb"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_pcs_pma_lvds"
   file="ethernet/tse_ucores/altera_eth_tse_pcs_pma_lvds/altera_eth_tse_pcs_pma_lvds_hw.tcl"
   displayName="altera_eth_tse_pcs_pma_lvds"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_pcs_pma_nf_lvds"
   file="ethernet/tse_ucores/altera_eth_tse_pcs_pma_nf_lvds/altera_eth_tse_pcs_pma_nf_lvds_hw.tcl"
   displayName="altera_eth_tse_pcs_pma_nf_lvds"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_pcs_pma_nf_phyip"
   file="ethernet/tse_ucores/altera_eth_tse_pcs_pma_nf_phyip/altera_eth_tse_pcs_pma_nf_phyip_hw.tcl"
   displayName="altera_eth_tse_pcs_pma_nf_phyip"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_pcs_pma_phyip"
   file="ethernet/tse_ucores/altera_eth_tse_pcs_pma_phyip/altera_eth_tse_pcs_pma_phyip_hw.tcl"
   displayName="altera_eth_tse_pcs_pma_phyip"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_tse_phyip_terminator"
   file="ethernet/tse_ucores/altera_eth_tse_phyip_terminator/altera_eth_tse_phyip_terminator_hw.tcl"
   displayName="altera_eth_tse_phyip_terminator"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_eth_valid_timestamp_detector"
   file="ethernet/ethernet_ucore/altera_eth_valid_timestamp_detector/altera_eth_valid_timestamp_detector_hw.tcl"
   displayName="Ethernet Valid Timestamp Detector"
   version="25.1"
   description="Altera Ethernet Valid Timestamp Detector"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_xgmii_crc"
   file="ethernet/ethernet_ucore/altera_eth_xgmii_crc/altera_eth_xgmii_crc_hw.tcl"
   displayName="Ethernet XGMII CRC"
   version="25.1"
   description="Altera Ethernet XGMII CRC"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
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  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_eth_xgmii_pipeline"
   file="ethernet/ethernet_ucore/altera_eth_xgmii_pipeline/altera_eth_xgmii_pipeline_hw.tcl"
   displayName="Ethernet XGMII Pipeline"
   version="25.1"
   description="Altera Ethernet XGMII Pipeline"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
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 <component
   name="altera_eth_xgmii_ptp_inserter"
   file="ethernet/ethernet_ucore/altera_eth_xgmii_ptp_inserter/altera_eth_xgmii_ptp_inserter_hw.tcl"
   displayName="Ethernet XGMII PTP Inserter"
   version="25.1"
   description="Altera Ethernet XGMII PTP Inserter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_eth_xgmii_termination"
   file="ethernet/ethernet_ucore/altera_eth_xgmii_termination/altera_eth_xgmii_termination_hw.tcl"
   displayName="Ethernet XGMII Termination"
   version="25.1"
   description="Altera Ethernet XGMII Termination"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
 </component>
 <component
   name="altera_eth_xgmii_tsu"
   file="ethernet/ethernet_ucore/altera_eth_xgmii_tsu/altera_eth_xgmii_tsu_hw.tcl"
   displayName="Ethernet XGMII TSU"
   version="25.1"
   description="Altera Ethernet XGMII TSU"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Submodules"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_external_memory_bfm"
   file="sopc_builder_ip/verification/altera_external_memory_bfm/altera_external_memory_bfm_hw.tcl"
   displayName="External Memory BFM Intel FPGA IP"
   version="25.1"
   description="Altera External Memory BFM"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471592433" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_fanout"
   file="sdi_ii/altera_fanout/altera_fanout_hw.tcl"
   displayName="Merlin Fanout"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II/Merlin Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
 </component>
 <component
   name="altera_fault_injection"
   file="altera_fault_injection/altera_fault_injection_hw.tcl"
   displayName="Fault Injection IP"
   version="25.1"
   description="Fault Injection enable customers to perform SEFI characterization in-house, scale FIT  rates according to SEFI characterization and optimize design to reduce effect of SEU."
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
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  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
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     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/esc1428515496663.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/tga1517813799038.html" />
 </component>
 <component
   name="altera_fft_ii"
   file="dsp/altera_fft_ii/altera_fft_ii_hw.tcl"
   displayName="FFT"
   version="25.1"
   description="Altera Fast Fourier Transform II"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="DSP/Transforms"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
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  <tag2
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  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_input" />
  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1419012539637/hco1419012438961" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697815758" />
 </component>
 <component
   name="altera_fir_compiler_ii"
   file="dsp/altera_fir_compiler_ii/src/HP_FIR_hw.tcl"
   displayName="FIR II"
   version="25.1"
   description="FIR II Intel FPGA IP"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=false"
   categories="DSP/Filters"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421694595728/hco1421694575632" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697809283" />
 </component>
 <component
   name="altera_fp_acc_custom"
   file="dsp/altera_fp_acc_custom/source/altera_fp_acc_custom_hw.tcl"
   displayName="FP_ACC_CUSTOM Intel FPGA IP"
   version="25.1"
   description="An application-specific floating point accumulator. A floating point accumulator that can be customized to the required range of input and output values. The accumulator will be built to operate at the target frequency on the target device family."
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Arithmetic"
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  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="VALIDATION_CALLBACK" value="validate_input" />
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_fp_functions"
   file="dsp/altera_fp_functions/source/altera_fp_hw.tcl"
   displayName="FP_FUNCTIONS Intel FPGA IP"
   version="25.1"
   description="A collection of floating point functions"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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     type="OTHER"
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 <component
   name="altera_fp_matrix_inv"
   file="dsp/altera_fp_matrix_inv/altera_fp_matrix_inv_hw.tcl"
   displayName="ALTERA_FP_MATRIX_INV"
   version="25.1"
   description="Altera Floating Point Matrix Invert"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
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  <documentUrl
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     type="OTHER"
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 </component>
 <component
   name="altera_fp_matrix_mult"
   file="dsp/altera_fp_matrix_mult/altera_fp_matrix_mult_hw.tcl"
   displayName="ALTERA_FP_MATRIX_MULT"
   version="25.1"
   description="Altera Floating Point Matrix Multiply"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
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  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
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  <documentUrl
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     type="OTHER"
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 </component>
 <component
   name="altera_fpdsp_block"
   file="dsp/altera_fpdsp_block/A10/FPDSP_hw.tcl"
   displayName="Native Floating Point DSP Intel Arria 10 FPGA IP"
   version="25.1"
   description="Altera Arria 10 FP DSP Block "
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="DSP/Primitive DSP"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
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  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_fpga_mii2rmii"
   file="intel_fpga_mii2rmii/intel_fpga_mii2rmii_hw.tcl"
   displayName="MII-to-RMII Converter IP"
   version="25.1"
   description="MII to RMII Converter core"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Hard Processor Components"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="altera_fpgamgr"
   file="hps/hard_peripheral_logical_view/fpgamgr/fpgamgr_hw.tcl"
   displayName="Altera FPGA Manager"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="altera_fxp_functions"
   file="dsp/altera_fxp_functions/altera_fxp_functions_hw.tcl"
   displayName="ALTERA_FXP_FUNCTIONS"
   version="25.1"
   description="A collection of fixed point functions"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade_callback" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="VHDL" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_input" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_altfp_mfug.pdf" />
 </component>
 <plugin
   name="altera_generic_quad_spi_controller"
   file="generic_qspi_controller/altera_generic_quad_spi_controller_sw.tcl"
   displayName="altera_generic_quad_spi_controller"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_generic_quad_spi_controller"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_generic_quad_spi_controller"
   file="generic_qspi_controller/generic_qspi_controller_hw.tcl"
   displayName="Generic QUAD SPI Controller IP"
   version="25.1"
   description="This component is a generic QSPI controller which allows user to access any QSPI devices"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=false"
   categories="Memory Interfaces and Controllers/Flash"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Cyclone V /// Arria V GZ /// Arria V /// Stratix V /// MAX 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1431459053861" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <plugin
   name="altera_generic_quad_spi_controller2"
   file="pgm/generic_qspi_controller2/altera_generic_quad_spi_controller2_sw.tcl"
   displayName="altera_generic_quad_spi_controller2"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_generic_quad_spi_controller2"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_generic_quad_spi_controller2"
   file="pgm/generic_qspi_controller2/generic_qspi_controller2_hw.tcl"
   displayName="Generic QUAD SPI controller II IP"
   version="25.1"
   description="This component is a generic QSPI controller which allows user to access any QSPI devices"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Memory Interfaces and Controllers/Flash"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Cyclone V /// Arria V GZ /// Arria V /// Stratix V /// MAX 10 /// Cyclone 10 LP /// Stratix 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html#rna1493925038164" />
 </component>
 <component
   name="altera_generic_tristate_controller"
   file="merlin/altera_generic_tristate_controller/altera_generic_tristate_controller_hw.tcl"
   displayName="Generic Tri-State Controller"
   version="25.1"
   description="Provides a template for a controller that you can parameterize to reflect the behavior of an off-chip device."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset,tristate_conduit"
   categories="Qsys Interconnect/Tri-State Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composed" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_avalon_tc.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409959350459" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <plugin
   name="altera_generic_tristate_controller.qprs"
   file="merlin/altera_generic_tristate_controller/altera_generic_tristate_controller.qprs"
   displayName="altera_generic_tristate_controller.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_generic_tristate_controller" />
 </plugin>
 <component
   name="altera_gmii_to_rgmii_adapter"
   file="altera_gmii_to_rgmii_adapter/altera_gmii_to_rgmii_adapter_wrapper_hw.tcl"
   displayName="HPS GMII to RGMII Converter IP"
   version="25.1"
   description="HPS GMII to RGMII Converter"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Hard Processor Components"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix 10 /// Arria 10 /// Arria V /// Cyclone V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683130/current/fpga-gmii-to-rgmii-converter-core.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683130/current/fpga-gmii-to-rgmii-converter-core-revision.html" />
 </component>
 <component
   name="altera_gmii_to_rgmii_adapter_core"
   file="altera_gmii_to_rgmii_adapter/altera_gmii_to_rgmii_adapter_hw.tcl"
   displayName="HPS GMII to RGMII Converter Core IP"
   version="25.1"
   description="HPS GMII to RGMII Converter core"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Processors and Peripherals/Hard Processor Components"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="Data Sheet "
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_embedded_ip.pdf" />
 </component>
 <component
   name="altera_gmii_to_sgmii_adapter"
   file="altera_gmii_to_sgmii_adapter/altera_gmii_to_sgmii_adapter_hw.tcl"
   displayName="HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge IP"
   version="25.1"
   description="HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Hard Processor Components"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix 10 /// Arria 10 /// Arria V /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="Data Sheet "
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_embedded_ip.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1434499254579" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_gpio"
   file="altera_gpio/altera_gpio_top/altera_gpio_hw.tcl"
   displayName="GPIO Intel FPGA IP"
   version="25.1"
   description="GPIO Intel FPGA IP"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/I/O"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="Altera GPIO user guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_altera_gpio.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_altera_gpio.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_gpio_core14"
   file="altera_gpio/altera_gpio_core14/altera_gpio_core_hw.tcl"
   displayName="Altera GPIO Core"
   version="25.1"
   description="Altera GPIO Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="I/O"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,QUARTUS_SYNTH,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_gpio_core20"
   file="altera_gpio/altera_gpio_core20/altera_gpio_core_hw.tcl"
   displayName="Altera GPIO Core"
   version="25.1"
   description="Altera GPIO Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="I/O"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,QUARTUS_SYNTH,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_gpio_driver"
   file="altera_gpio/altera_gpio_driver/altera_gpio_driver_hw.tcl"
   displayName="Altera GPIO Driver"
   version="25.1"
   description="Altera GPIO Driver"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="I/O"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_gpio_lite"
   file="altera_gpio_lite/altera_gpio_lite_hw.tcl"
   displayName="GPIO Lite Intel FPGA IP"
   version="25.1"
   description="GPIO Lite Intel FPGA IP"
   tags="AUTHORSHIP=Intel Corporation"
   categories="Basic Functions/I/O"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="MAX 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/en_US/pdfs/literature/hb/max-10/ug_m10_gpio.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_hdmi"
   file="altera_hdmi/src/common/altera_hdmi_hw.tcl"
   displayName="HDMI Intel FPGA IP"
   version="25.1"
   description="HDMI Intel FPGA IP"
   tags="AUTHORSHIP=Intel Corporation"
   categories="Interface Protocols/Audio &amp; Video"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria V /// Stratix V /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_callback" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/vgo1401099304599.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/hco1421697823968.html" />
  <documentUrl
     displayName="Design Example User Guide for Intel Arria 10"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/aky1476080261496.html" />
 </component>
 <component
   name="altera_hmcc"
   file="altera_hmcc/altera_hmcc/altera_hmcc_hw.tcl"
   displayName="Hybrid Memory Cube Controller"
   version="25.1"
   description="Altera Hybrid Memory Cube Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Memory Interfaces and Controllers"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_hmcc.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412377950681/nik1412377908032" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/ewo1424301491510" />
 </component>
 <component
   name="altera_hmcc_mtaps"
   file="altera_hmcc_mtaps/altera_hmcc_mtaps/altera_hmcc_mtaps_hw.tcl"
   displayName="Hybrid Memory Cube Controller"
   version="25.1"
   description="Altera Hybrid Memory Cube Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Memory Interfaces and Controllers"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2
     key="UPGRADEABLE_FROM"
     value="altera_hmcc/15.1/Arria 10 /// altera_hmcc/15.0/Arria 10" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_proc" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_hmcc.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412377950681/nik1412377908032" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/ewo1424301491510" />
  <documentUrl
     displayName="Example Design"
     type="OTHER"
     url="https://www.altera.com/en_US/pdfs/literature/ug/deug_hmcc.pdf" />
 </component>
 <component
   name="altera_hps"
   file="hps/altera_hps/altera_hps_hw.tcl"
   displayName="Arria V/Cyclone V Hard Processor System"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Processors and Peripherals/Hard Processor Systems"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="STRUCTURAL_COMPOSITION_CALLBACK" value="compose_logicalview" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Cyclone V /// Arria V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <documentUrl
     displayName="HPS User Guide for Cyclone V"
     type="OTHER"
     url="http://www.altera.com/literature/hb/cyclone-v/cv_5v4.pdf" />
  <documentUrl
     displayName="HPS User Guide for Arria V"
     type="OTHER"
     url="http://www.altera.com/literature/hb/arria-v/av_5v4.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/products/soc/overview.html" />
 </component>
 <plugin
   name="altera_hps_ddr2.qprs"
   file="hps/altera_hps/altera_hps_ddr2.qprs"
   displayName="altera_hps_ddr2.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_hps" />
 </plugin>
 <plugin
   name="altera_hps_ddr3.qprs"
   file="hps/altera_hps/altera_hps_ddr3.qprs"
   displayName="altera_hps_ddr3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_hps" />
 </plugin>
 <component
   name="altera_hps_emac_interface_splitter"
   file="altera_hps_emac_interface_splitter/altera_hps_emac_interface_splitter_hw.tcl"
   displayName="HPS Emac Interface Splitter IP"
   version="25.1"
   description="HPS Emac Interface Splitter core"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Hard Processor Components"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix 10 /// Arria 10 /// Arria V /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="Data Sheet "
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_embedded_ip.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1434499254579" />
 </component>
 <component
   name="altera_hps_io"
   file="hps/altera_hps_io/altera_hps_io_hw.tcl"
   displayName="altera_hps_io"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Cyclone V /// Arria V" />
  <tag2 key="SUPPRESS_WARNINGS" value="NO_PORTS_AFTER_ELABORATION" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <plugin
   name="altera_hps_lpddr2.qprs"
   file="hps/altera_hps/altera_hps_lpddr2.qprs"
   displayName="altera_hps_lpddr2.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_hps" />
 </plugin>
 <component
   name="altera_hps_master_bfm"
   file="sopc_builder_ip/verification/altera_hps_master_bfm/altera_hps_master_bfm_hw.tcl"
   displayName="Altera HPS Master BFM"
   version="11.1"
   description="Altera HPS Master BFM"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_hps_slave_bfm"
   file="sopc_builder_ip/verification/altera_hps_slave_bfm/altera_hps_slave_bfm_hw.tcl"
   displayName="Altera HPS Slave BFM"
   version="11.1"
   description="Altera HPS Slave BFM"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_i2cslave_to_avlmm_bridge"
   file="sopc_builder_ip/altera_i2cslave_to_avlmm_bridge/altera_i2cslave_to_avlmm_bridge_hw.tcl"
   displayName="I2C Slave To Avalon-MM Master Bridge IP"
   version="25.1"
   description="I2C Slave To Avalon Master Bridge is a collection of pre-wired components that provide an Avalon Master using an external I2C interface"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Peripherals"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.1" />
 </component>
 <component
   name="altera_in_system_sources_probes"
   file="sld/jtag/altera_in_system_sources_probes/altera_in_system_sources_probes_hw.tcl"
   displayName="Intel FPGA In-System Sources &amp; Probes"
   version="25.1"
   description="In-system sources &amp; probes debugging megafunction.  The In-System Sources and Probes megafunction is
available for all Intel FPGA device families supported by the Quartus Prime software."
   tags="AUTHORSHIP=Intel Corporation"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="do_elaboration" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="HardCopy II /// APEX20K /// Cyclone V /// MAX9000 /// HardCopy III /// HardCopy IV /// Cyclone 10 LP /// EPC1 /// EPC2 /// eFPGA 28 HPM /// Programmer Dummy Family /// Cyclone IV E /// MAX V /// FLEX6000 /// Arria 10 /// Cyclone III LS /// FLEX10KE /// Soc Series V /// Stratix 10 for Emulator Use /// Arria II GX /// APEX II /// Arria II GZ /// Cyclone II /// FLEX10KB /// FLEX10KA /// Stratix /// MAX7000AE /// Stratix GX /// Cyclone III /// MAX3000A /// ALTERA /// Cyclone IV GX /// Enhanced Configuration Devices /// MAX 10 /// HardCopy Stratix /// MAX II /// Stratix III /// Arria V GZ /// MAX7000S /// Virtual JTAG TAP /// EMBEDDED_PROCESSOR /// ASC devices /// Cyclone /// Stratix II /// Stratix 10 /// FLEX10K /// FLEX8000 /// EXCALIBUR_ARM /// Stratix V /// MAX7000B /// MAX7000A /// ACEX1K /// APEX20KC /// Stratix II GX /// APEX20KE /// Arria GX /// Flash Memory /// Arria V /// None /// Mercury /// Stratix IV" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="Quartus II Handbook Volume 3: Verification"
     type="OTHER"
     url="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii5v3.pdf" />
  <documentUrl
     displayName="altsource_probe Megafunction Online Help"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/lit-index.html#/link/mwh1410385117325/mwh1410384945607" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/lit-index.html#/link/mwh1410385117325/mwh1410384945607" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-debug.pdf" />
 </component>
 <component
   name="altera_instrumentation_mirror_endpoint"
   file="sld/core/endpoint_wrappers/altera_instrumentation_mirror_endpoint_hw.tcl"
   displayName="altera_instrumentation_mirror_endpoint"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_int_osc"
   file="altera_int_osc/altera_int_osc_hw.tcl"
   displayName="Internal Oscillator IP"
   version="25.1"
   description="Internal Oscillator provides internal clock source for debugging purpose."
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// MAX 10 /// Arria V GZ /// Arria V /// Arria II GX /// Arria 10 /// Cyclone V /// Cyclone IV GX /// Cyclone IV E /// Cyclone 10 LP" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
 </component>
 <component
   name="altera_interface_generator"
   file="hps/altera_interface_generator/altera_interface_generator_hw.tcl"
   displayName="altera_interface_generator"
   version="25.1"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="SUPPRESS_WARNINGS" value="NO_PORTS_AFTER_ELABORATION" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="altera_iopll"
   file="altera_iopll/top/altera_iopll_hw.tcl"
   displayName="IOPLL Intel FPGA IP"
   version="25.1"
   description="Intel Phase-Locked Loop"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Clocks; PLLs and Resets/PLL"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="parameter_upgrade_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Stratix 10 for Emulator Use" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2
     key="UPGRADEABLE_FROM"
     value="altera_pll/13.1/Arria 10 /// altera_pll/14.0/Arria 10 /// altera_pll/12.0/Stratix V /// altera_pll/12.1/Stratix V /// altera_pll/13.0/Stratix V /// altera_pll/13.1/Stratix V /// altera_pll/14.0/Stratix V /// altera_pll/12.0/Arria V /// altera_pll/12.1/Arria V /// altera_pll/13.0/Arria V /// altera_pll/13.1/Arria V /// altera_pll/14.0/Arria V /// altera_pll/12.0/Cyclone V /// altera_pll/12.1/Cyclone V /// altera_pll/13.0/Cyclone V /// altera_pll/13.1/Cyclone V /// altera_pll/14.0/Cyclone V" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altera_iopll.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mcn1403678389838/mcn1403678554052" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://dopertocumentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_iopll_inst_10g"
   file="seriallite_iii/example/example_design/demo_control/altera_iopll_inst_10g.qsys"
   displayName="altera_iopll_inst_10g"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_iopll_inst_12g"
   file="seriallite_iii/example/example_design/demo_control/altera_iopll_inst_12g.qsys"
   displayName="altera_iopll_inst_12g"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_iopll_reconfig"
   file="altera_iopll_reconfig/iopll_reconfig_hw.tcl"
   displayName="IOPLL Reconfig Intel FPGA IP"
   version="25.1"
   description="Intel Phase-Locked Loop Reconfiguration Block"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Clocks; PLLs and Resets/PLL"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10 for Emulator Use" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
  <documentUrl displayName="DATASHEET" type="DATASHEET" url="" />
 </component>
 <component
   name="altera_ip_col_if"
   file="emif/ip_col_if/altera_ip_col_if_hw.tcl"
   displayName="External Memory Interfaces Debug Component"
   version="25.1"
   description="This component must be connected to one of the EMIF cores in an I/O column in order to access it using the External Memory Interface Debug Toolkit."
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Memory Interfaces and Controllers"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="COMPOSITION_CALLBACK"
     value="::altera_emif::ip_col_if::main::composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/hb/external-memory/emi.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697745716" />
 </component>
 <component
   name="altera_irq_bridge"
   file="merlin/altera_irq_bridge/altera_irq_bridge_hw.tcl"
   displayName="IRQ Bridge"
   version="25.1"
   description="Allows you to route interrupt wires between Qsys subsystems."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,interrupt,reset"
   categories="Basic Functions/Bridges and Adaptors/Interrupt"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958933301" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_irq_clock_crosser"
   file="merlin/altera_irq_clock_crosser/altera_irq_clock_crosser_hw.tcl"
   displayName="Merlin IRQ Clock Crosser"
   version="25.1"
   description="Synchronizes interrupt senders and receivers that are in different clock domains."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,interrupt,reset"
   categories="Qsys Interconnect/Interrupt"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_irq_fanout"
   file="merlin/altera_irq_fanout/altera_irq_fanout_hw.tcl"
   displayName="Merlin IRQ Fanout"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Qsys Interconnect/Interrupt"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_irq_mapper"
   file="merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl"
   displayName="Merlin IRQ Mapper"
   version="25.1"
   description="Converts individual interrupt wires to a bus. By default, the interrupt sender connected to the receiver0 interface of the IRQ mapper is the highest priority with sequential receivers beiing successively lower priority."
   tags="AUTHORSHIP=Altera Corporation"
   categories="Qsys Interconnect/Interrupt"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
 </component>
 <component
   name="altera_jesd204"
   file="altera_jesd204/src/top/altera_jesd204_hw.tcl"
   displayName="JESD204B IP"
   version="25.1"
   description="JESD204B IP"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="my_compose_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix 10 /// Arria 10 /// Stratix V /// Arria V GZ /// Arria V /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="my_validation_callback" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_jesd204b.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411117158599/bhc1411116797881" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697842482" />
 </component>
 <component
   name="altera_jesd204_fanout"
   file="altera_jesd204/src/lib/altera_jesd204_fanout/altera_jesd204_fanout_hw.tcl"
   displayName="JESD204B Fanout"
   version="25.1"
   description="Altera JESD204 Fanout"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
 </component>
 <component
   name="altera_jesd204_phy"
   file="altera_jesd204/src/lib/phy_top/altera_jesd204_phy_hw.tcl"
   displayName="JESD204B PHY wrapper"
   version="25.1"
   description="JESD204B MegaCore Function"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="my_compose_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="my_validation_callback" />
 </component>
 <component
   name="altera_jesd204_phy_adapter"
   file="altera_jesd204/src/lib/phy_adapter/altera_jesd204_phy_adapter_hw.tcl"
   displayName="JESD204B PHY Adapter"
   version="25.1"
   description="JESD204B PHY Adapter"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_jesd204_phy_adapter_xs"
   file="altera_jesd204/src/lib/phy_adapter/altera_jesd204_phy_adapter_xs_hw.tcl"
   displayName="JESD204B PHY Adapter XS"
   version="25.1"
   description="JESD204B PHY Adapter for 10th Series"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_jesd204_phy_adapter_xs_rcfg_shared_off"
   file="altera_jesd204/src/lib/phy_adapter/altera_jesd204_phy_adapter_xs_rcfg_shared_off_hw.tcl"
   displayName="JESD204B PHY Adapter XS RCFG_SHARED OFF"
   version="25.1"
   description="JESD204B PHY Adapter for 10th Series"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_jesd204_pll_wrapper"
   file="altera_jesd204/src/lib/pll_wrapper/altera_jesd204_pll_hw.tcl"
   displayName="JESD204B PLL Wrapper"
   version="25.1"
   description="JESD204B PLL wrapper"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="my_compose_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_jesd204_rx"
   file="altera_jesd204/src/rx/altera_jesd204_rx_hw.tcl"
   displayName="JESD204B RX"
   version="25.1"
   description="JESD204B MegaCore Function"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_jesd204_rx_mlpcs"
   file="altera_jesd204/src/rx_mlpcs/altera_jesd204_rx_mlpcs_hw.tcl"
   displayName="JESD204B RX MLPCS"
   version="25.1"
   description="JESD204B MegaCore Function"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_jesd204_signal_adapter"
   file="altera_jesd204/src/lib/sig_adapter/altera_jesd204_signal_adapter_hw.tcl"
   displayName="JESD204B Signal Adapter"
   version="25.1"
   description="JESD204B Signal Adapter"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_jesd204_tx"
   file="altera_jesd204/src/tx/altera_jesd204_tx_hw.tcl"
   displayName="JESD204B TX"
   version="25.1"
   description="JESD204B MegaCore Function"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_jesd204_tx_mlpcs"
   file="altera_jesd204/src/tx_mlpcs/altera_jesd204_tx_mlpcs_hw.tcl"
   displayName="JESD204B TX MLPCS"
   version="25.1"
   description="JESD204B MegaCore Function"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/JESD"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="altera_jtag_avalon_master"
   file="sopc_builder_ip/altera_jtag_avalon_master/altera_jtag_avalon_master_hw.tcl"
   displayName="JTAG to Avalon Master Bridge"
   version="25.1"
   description="The JTAG to Avalon Master Bridge is a collection of pre-wired components that provide an Avalon Master using the new JTAG channel."
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Bridges and Adaptors/Memory Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/nios2/qts_qii55011.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401396548170" />
 </component>
 <component
   name="altera_jtag_avalon_master_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE/rtl/jtag_avalon_master/altera_jtag_avalon_master_a10.qsys"
   displayName="altera_jtag_avalon_master_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_jtag_avalon_master_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/jtag_avalon_master/altera_jtag_avalon_master_a10.qsys"
   displayName="altera_jtag_avalon_master_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_jtag_avalon_master_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE/rtl/jtag_avalon_master/altera_jtag_avalon_master_a10.qsys"
   displayName="altera_jtag_avalon_master_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_jtag_avalon_master_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/jtag_avalon_master/altera_jtag_avalon_master_a10.qsys"
   displayName="altera_jtag_avalon_master_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_jtag_dc_streaming"
   file="sopc_builder_ip/altera_avalon_jtag_phy/altera_avalon_st_jtag_interface_hw.tcl"
   displayName="Avalon-ST JTAG Interface"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Serial"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/nios2/qts_qii55008.pdf" />
 </component>
 <component
   name="altera_jtag_debug_link"
   file="sld/jtag/altera_jtag_debug_link/altera_jtag_debug_link_hw.tcl"
   displayName="JTAG Debug Link"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_jtag_debug_link_internal"
   file="sld/jtag/altera_jtag_debug_link/altera_jtag_debug_link_internal_hw.tcl"
   displayName="JTAG Debug Link (internal module)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_jtag_pins_bridge"
   file="sld/jtag/altera_jtag_pins_bridge/altera_jtag_pins_bridge_hw.tcl"
   displayName="altera_jtag_pins_bridge"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_jtag_wys_atom"
   file="sld/jtag/altera_jtag_wys_atom/altera_jtag_wys_atom_hw.tcl"
   displayName="altera_jtag_wys_atom"
   version="25.1"
   description="Altera JTAG to PLD core interface"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_l3regs"
   file="hps/hard_peripheral_logical_view/l3regs/l3regs_hw.tcl"
   displayName="Altera HPS L3 Registers"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="altera_lauterbach_trace_interface_ip"
   file="altera_lauterbach_trace_ip/altera_lauterbach_nios2_offchip_trace_buffer_hw.tcl"
   displayName="Lauterbach Trace Interface IP"
   version="25.1"
   description="Lauterbach Nios II Trace Interface IP"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Peripherals"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.lauterbach.com/frames.html?bdmnios.html" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.lauterbach.com/frames.html?bdmnios.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_logic_analyzer_interface_agent"
   file="sld/jtag/altera_logic_analyzer_interface_agent/altera_logic_analyzer_interface_agent_hw.tcl"
   displayName="Altera Logic Analyzer Interface Agent"
   version="25.1"
   description="Altera Logic Analyzer Interface Agent"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="do_elaboration" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="HardCopy II /// APEX20K /// Cyclone V /// MAX9000 /// HardCopy III /// HardCopy IV /// Cyclone 10 LP /// EPC1 /// EPC2 /// eFPGA 28 HPM /// Programmer Dummy Family /// Cyclone IV E /// MAX V /// FLEX6000 /// Arria 10 /// Cyclone III LS /// FLEX10KE /// Soc Series V /// Stratix 10 for Emulator Use /// Arria II GX /// APEX II /// Arria II GZ /// Cyclone II /// FLEX10KB /// FLEX10KA /// Stratix /// MAX7000AE /// Stratix GX /// Cyclone III /// MAX3000A /// ALTERA /// Cyclone IV GX /// Enhanced Configuration Devices /// MAX 10 /// HardCopy Stratix /// MAX II /// Stratix III /// Arria V GZ /// MAX7000S /// Virtual JTAG TAP /// EMBEDDED_PROCESSOR /// ASC devices /// Cyclone /// Stratix II /// Stratix 10 /// FLEX10K /// FLEX8000 /// EXCALIBUR_ARM /// Stratix V /// MAX7000B /// MAX7000A /// ACEX1K /// APEX20KC /// Stratix II GX /// APEX20KE /// Arria GX /// Flash Memory /// Arria V /// None /// Mercury /// Stratix IV" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="altera_lpddr2_board_delay_model"
   file="alt_mem_if/ed_comps/board_delay_models/altera_lpddr2_board_delay_model/altera_lpddr2_board_delay_model_hw.tcl"
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   description="Altera DDR2 Sequencer Mux Bridge"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_afi_gasket"
   file="alt_mem_if/alt_mem_if_multirank_gasket/alt_mem_if_ddr3_multirank_gasket/alt_mem_if_ddr3_multirank_gasket_hw.tcl"
   displayName="Altera DDR3 AFI Gasket"
   version="25.1"
   description="Altera DDR3 AFI Gasket"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Gaskets"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_afi_mux"
   file="alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_ddr3_afi_mux/altera_mem_if_ddr3_afi_mux_hw.tcl"
   displayName="Altera DDR3 AFI Multiplexer"
   version="25.1"
   description="Altera DDR3 AFI Multiplexer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_afi_splitter"
   file="alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_ddr3_afi_splitter/altera_mem_if_ddr3_afi_splitter_hw.tcl"
   displayName="UniPHY DDR3 AFI Splitter"
   version="25.1"
   description="UniPHY DDR3 AFI Splitter"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_controller"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_ddr3_controller/alt_mem_if_ddr3_controller_hw.tcl"
   displayName="Altera DDR3 Memory Controller"
   version="25.1"
   description="Altera DDR3 Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_emif"
   file="alt_mem_if/alt_mem_if_interfaces/alt_mem_if_ddr3_emif/alt_mem_if_ddr3_emif_hw.tcl"
   displayName="DDR3 SDRAM Controller with UniPHY IP"
   version="25.1"
   description="DDR3 SDRAM Controller with UniPHY IP"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="ip_compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Stratix IV /// Stratix III /// Arria II GZ /// Arria V /// Arria V GZ /// Cyclone V /// MAX 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/external-memory/emi.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697797999" />
 </component>
 <component
   name="altera_mem_if_ddr3_hard_memory_controller"
   file="alt_mem_if/alt_mem_if_controllers/altera_mem_if_ddr3_hard_memory_controller/altera_mem_if_ddr3_hard_memory_controller_hw.tcl"
   displayName="Altera DDR3 Hard Memory Controller"
   version="25.1"
   description="Altera DDR3 Hard Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_hard_phy_core"
   file="alt_mem_if/alt_mem_if_phys/alt_mem_if_ddr3_hard_phy_core/altera_mem_if_ddr3_hard_phy_core_hw.tcl"
   displayName="DDR3 SDRAM External Memory Hard PHY Core"
   version="25.1"
   description="DDR3 SDRAM External Memory Hard PHY Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_mem_model"
   file="alt_mem_if/alt_mem_if_mem_models/alt_mem_if_ddr3_mem_model/alt_mem_if_ddr3_mem_model_hw.tcl"
   displayName="Altera DDR3 Memory Model for UniPHY"
   version="25.1"
   description="Altera DDR3 Memory Model for UniPHY"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Models"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_phy_core"
   file="alt_mem_if/alt_mem_if_phys/alt_mem_if_ddr3_phy_core/altera_mem_if_ddr3_phy_core_hw.tcl"
   displayName="DDR3 SDRAM External Memory PHY"
   version="25.1"
   description="DDR3 SDRAM External Memory PHY"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_pll"
   file="alt_mem_if/altera_mem_if_pll/altera_mem_if_ddr3_pll/altera_mem_if_ddr3_pll_hw.tcl"
   displayName="DDR3 SDRAM External Memory PLL/DLL/OCT block"
   version="25.1"
   description="DDR3 SDRAM External Memory PLL/DLL/OCT block"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_qseq"
   file="alt_mem_if/altera_mem_if_qseq/altera_mem_if_ddr3_qseq/altera_mem_if_ddr3_qseq_hw.tcl"
   displayName="DDR3 SDRAM Qsys Sequencer"
   version="25.1"
   description="DDR3 SDRAM Qsys Sequencer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_ddr3_seq_mux_bridge"
   file="alt_mem_if/bridges/seq_mux_bridges/altera_mem_if_ddr3_seq_mux_bridge/altera_mem_if_ddr3_seq_mux_bridge_hw.tcl"
   displayName="Altera DDR3 Sequencer Mux Bridge"
   version="25.1"
   description="Altera DDR3 Sequencer Mux Bridge"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_dll"
   file="alt_mem_if/altera_mem_if_dll/altera_mem_if_dll_hw.tcl"
   displayName="External Memory DLL block"
   version="25.1"
   description="External Memory DLL block"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_dll_bridge"
   file="alt_mem_if/altera_mem_if_dll_bridge/altera_mem_if_dll_bridge_hw.tcl"
   displayName="External Memory DLL block bridge"
   version="25.1"
   description="External Memory DLL block bridge"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_fake_ddr2_phy"
   file="alt_mem_if/alt_mem_if_phys/alt_mem_if_fake_ddr2_phy/alt_mem_if_fake_ddr2_phy_hw.tcl"
   displayName="Fake DDR2 SDRAM External Memory PHY"
   version="25.1"
   description="Fake DDR2 SDRAM External Memory PHY"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_fake_ddr3_phy"
   file="alt_mem_if/alt_mem_if_phys/alt_mem_if_fake_ddr3_phy/alt_mem_if_fake_ddr3_phy_hw.tcl"
   displayName="Fake DDR3 SDRAM External Memory PHY"
   version="25.1"
   description="Fake DDR3 SDRAM External Memory PHY"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
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  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_hcx_rom_reconfig_gen"
   file="alt_mem_if/alt_mem_if_example_design_components/alt_mem_if_hcx_rom_reconfig_gen/alt_mem_if_hcx_rom_reconfig_gen_hw.tcl"
   displayName="HCx ROM Reconfig Generator"
   version="25.1"
   description="UniPHY HCx ROM Reconfig Generator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Example Design Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="altera_mem_if_hhp_ddr2_qseq"
   file="alt_mem_if/altera_mem_if_qseq/altera_mem_if_hhp_qseq/altera_mem_if_hhp_ddr2_qseq_hw.tcl"
   displayName="HHP/HPS Sequencer"
   version="25.1"
   description="HHP/HPS Sequencer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_hhp_ddr3_qseq"
   file="alt_mem_if/altera_mem_if_qseq/altera_mem_if_hhp_qseq/altera_mem_if_hhp_ddr3_qseq_hw.tcl"
   displayName="HHP/HPS Sequencer"
   version="25.1"
   description="HHP/HPS Sequencer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
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  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_hhp_lpddr2_qseq"
   file="alt_mem_if/altera_mem_if_qseq/altera_mem_if_hhp_qseq/altera_mem_if_hhp_lpddr2_qseq_hw.tcl"
   displayName="HHP/HPS Sequencer"
   version="25.1"
   description="HHP/HPS Sequencer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_hps_ddr2_memory_controller"
   file="alt_mem_if/alt_mem_if_controllers/altera_mem_if_hps_memory_controller/altera_mem_if_hps_ddr2_memory_controller_hw.tcl"
   displayName="Altera HPS DDR2 Memory Controller"
   version="25.1"
   description="Altera HPS DDR2 Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
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  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
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 <component
   name="altera_mem_if_hps_ddr3_memory_controller"
   file="alt_mem_if/alt_mem_if_controllers/altera_mem_if_hps_memory_controller/altera_mem_if_hps_ddr3_memory_controller_hw.tcl"
   displayName="Altera HPS DDR3 Memory Controller"
   version="25.1"
   description="Altera HPS DDR3 Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
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 <component
   name="altera_mem_if_hps_emif"
   file="alt_mem_if/alt_mem_if_interfaces/alt_mem_if_hps_emif/altera_mem_if_hps_emif_hw.tcl"
   displayName="HPS DDRx SDRAM Controller with UniPHY IP"
   version="25.1"
   description="HPS DDRx SDRAM Controller with UniPHY IP"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="ip_compose" />
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  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
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  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
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  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
  <documentUrl
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     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
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 <component
   name="altera_mem_if_hps_lpddr2_memory_controller"
   file="alt_mem_if/alt_mem_if_controllers/altera_mem_if_hps_memory_controller/altera_mem_if_hps_lpddr2_memory_controller_hw.tcl"
   displayName="Altera HPS LPDDR2 Memory Controller"
   version="25.1"
   description="Altera HPS LPDDR2 Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_hps_pll"
   file="alt_mem_if/altera_mem_if_pll/altera_mem_if_hps_pll/altera_mem_if_hps_pll_hw.tcl"
   displayName="HPS SDRAM External Memory PLL block"
   version="25.1"
   description="HPS SDRAM External Memory PLL block"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr2_afi_mux"
   file="alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_lpddr2_afi_mux/altera_mem_if_lpddr2_afi_mux_hw.tcl"
   displayName="Altera LPDDR2 AFI Multiplexer"
   version="25.1"
   description="Altera LPDDR2 AFI Multiplexer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr2_afi_splitter"
   file="alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_lpddr2_afi_splitter/altera_mem_if_lpddr2_afi_splitter_hw.tcl"
   displayName="UniPHY LPDDR2 AFI Splitter"
   version="25.1"
   description="UniPHY LPDDR2 AFI Splitter"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
   factory="TclModuleFactory">
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  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr2_controller"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_lpddr2_controller/alt_mem_if_lpddr2_controller_hw.tcl"
   displayName="Altera LPDDR2 Memory Controller"
   version="25.1"
   description="Altera LPDDR2 Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
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  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr2_emif"
   file="alt_mem_if/alt_mem_if_interfaces/alt_mem_if_lpddr2_emif/alt_mem_if_lpddr2_emif_hw.tcl"
   displayName="LPDDR2 SDRAM Controller with UniPHY IP"
   version="25.1"
   description="LPDDR2 SDRAM Controller with UniPHY IP"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY"
   factory="TclModuleFactory">
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  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2
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     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
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     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/external-memory/emi.pdf" />
 </component>
 <component
   name="altera_mem_if_lpddr2_hard_memory_controller"
   file="alt_mem_if/alt_mem_if_controllers/altera_mem_if_lpddr2_hard_memory_controller/altera_mem_if_lpddr2_hard_memory_controller_hw.tcl"
   displayName="Altera LPDDR2 Hard Memory Controller"
   version="25.1"
   description="Altera LPDDR2 Hard Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
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  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr2_hard_phy_core"
   file="alt_mem_if/alt_mem_if_phys/alt_mem_if_lpddr2_hard_phy_core/altera_mem_if_lpddr2_hard_phy_core_hw.tcl"
   displayName="LPDDR2 SDRAM External Memory Hard PHY Core"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
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  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr2_mem_model"
   file="alt_mem_if/alt_mem_if_mem_models/alt_mem_if_lpddr2_mem_model/alt_mem_if_lpddr2_mem_model_hw.tcl"
   displayName="Altera LPDDR2 Memory Model for UniPHY"
   version="25.1"
   description="Altera LPDDR2 Memory Model for UniPHY"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Models"
   factory="TclModuleFactory">
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 </component>
 <component
   name="altera_mem_if_lpddr2_phy_core"
   file="alt_mem_if/alt_mem_if_phys/alt_mem_if_lpddr2_phy_core/altera_mem_if_lpddr2_phy_core_hw.tcl"
   displayName="LPDDR2 SDRAM External Memory PHY"
   version="25.1"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
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  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr2_pll"
   file="alt_mem_if/altera_mem_if_pll/altera_mem_if_lpddr2_pll/altera_mem_if_lpddr2_pll_hw.tcl"
   displayName="LPDDR2 SDRAM External Memory PLL/DLL/OCT block"
   version="25.1"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
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  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr2_qseq"
   file="alt_mem_if/altera_mem_if_qseq/altera_mem_if_lpddr2_qseq/altera_mem_if_lpddr2_qseq_hw.tcl"
   displayName="LPDDR2 SDRAM Qsys Sequencer"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencers"
   factory="TclModuleFactory">
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  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr2_seq_mux_bridge"
   file="alt_mem_if/bridges/seq_mux_bridges/altera_mem_if_lpddr2_seq_mux_bridge/altera_mem_if_lpddr2_seq_mux_bridge_hw.tcl"
   displayName="Altera LPDDR2 Sequencer Mux Bridge"
   version="25.1"
   description="Altera LPDDR2 Sequencer Mux Bridge"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
   factory="TclModuleFactory">
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 <component
   name="altera_mem_if_lpddr_afi_mux"
   file="alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_lpddr_afi_mux/altera_mem_if_lpddr_afi_mux_hw.tcl"
   displayName="Altera LPDDR AFI Multiplexer"
   version="25.1"
   description="Altera LPDDR AFI Multiplexer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr_afi_splitter"
   file="alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_lpddr_afi_splitter/altera_mem_if_lpddr_afi_splitter_hw.tcl"
   displayName="UniPHY LPDDR AFI Splitter"
   version="25.1"
   description="UniPHY LPDDR AFI Splitter"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
   factory="TclModuleFactory">
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  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr_hard_memory_controller"
   file="alt_mem_if/alt_mem_if_controllers/altera_mem_if_lpddr_hard_memory_controller/altera_mem_if_lpddr_hard_memory_controller_hw.tcl"
   displayName="Altera LPDDR Hard Memory Controller"
   version="25.1"
   description="Altera LPDDR Hard Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria V /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr_hard_phy_core"
   file="alt_mem_if/alt_mem_if_phys/alt_mem_if_lpddr_hard_phy_core/altera_mem_if_lpddr_hard_phy_core_hw.tcl"
   displayName="LPDDR SDRAM External Memory Hard PHY Core"
   version="25.1"
   description="LPDDR SDRAM External Memory Hard PHY Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr_mem_model"
   file="alt_mem_if/alt_mem_if_mem_models/alt_mem_if_lpddr_mem_model/alt_mem_if_lpddr_mem_model_hw.tcl"
   displayName="Altera LPDDR Memory Model for UniPHY"
   version="25.1"
   description="Altera LPDDR Memory Model for UniPHY"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Models"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr_phy_core"
   file="alt_mem_if/alt_mem_if_phys/alt_mem_if_lpddr_phy_core/altera_mem_if_lpddr_phy_core_hw.tcl"
   displayName="LPDDR SDRAM External Memory PHY"
   version="25.1"
   description="LPDDR SDRAM External Memory PHY"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr_pll"
   file="alt_mem_if/altera_mem_if_pll/altera_mem_if_lpddr_pll/altera_mem_if_lpddr_pll_hw.tcl"
   displayName="LPDDR SDRAM External Memory PLL/DLL/OCT block"
   version="25.1"
   description="LPDDR SDRAM External Memory PLL/DLL/OCT block"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr_qseq"
   file="alt_mem_if/altera_mem_if_qseq/altera_mem_if_lpddr_qseq/altera_mem_if_lpddr_qseq_hw.tcl"
   displayName="LPDDR SDRAM Qsys Sequencer"
   version="25.1"
   description="LPDDR SDRAM Qsys Sequencer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_lpddr_seq_mux_bridge"
   file="alt_mem_if/bridges/seq_mux_bridges/altera_mem_if_lpddr_seq_mux_bridge/altera_mem_if_lpddr_seq_mux_bridge_hw.tcl"
   displayName="Altera LPDDR Sequencer Mux Bridge"
   version="25.1"
   description="Altera LPDDR Sequencer Mux Bridge"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_nextgen_ddr2_controller"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr2_controller/alt_mem_if_nextgen_ddr2_controller_hw.tcl"
   displayName="Altera DDR2 Nextgen Memory Controller"
   version="25.1"
   description="Altera DDR2 Nextgen Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="ip_compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_nextgen_ddr2_controller_core"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr2_controller_core/alt_mem_if_nextgen_ddr2_controller_core_hw.tcl"
   displayName="Altera DDR2 Nextgen Memory Controller Core"
   version="25.1"
   description="Altera DDR2 Nextgen Memory Controller Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controller Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_nextgen_ddr3_controller"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller/alt_mem_if_nextgen_ddr3_controller_hw.tcl"
   displayName="Altera DDR3 Nextgen Memory Controller"
   version="25.1"
   description="Altera DDR3 Nextgen Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="ip_compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_nextgen_ddr3_controller_core"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_ddr3_controller_core/alt_mem_if_nextgen_ddr3_controller_core_hw.tcl"
   displayName="Altera DDR3 Nextgen Memory Controller Core"
   version="25.1"
   description="Altera DDR3 Nextgen Memory Controller Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controller Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_nextgen_lpddr2_controller"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_lpddr2_controller/alt_mem_if_nextgen_lpddr2_controller_hw.tcl"
   displayName="Altera LPDDR2 Nextgen Memory Controller"
   version="25.1"
   description="Altera LPDDR2 Nextgen Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="ip_compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_nextgen_lpddr2_controller_core"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_lpddr2_controller_core/alt_mem_if_nextgen_lpddr2_controller_core_hw.tcl"
   displayName="Altera LPDDR2 Nextgen Memory Controller Core"
   version="25.1"
   description="Altera LPDDR2 Nextgen Memory Controller Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controller Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria V /// Cyclone V /// MAX 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_nextgen_lpddr_controller"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_lpddr_controller/alt_mem_if_nextgen_lpddr_controller_hw.tcl"
   displayName="Altera LPDDR Nextgen Memory Controller"
   version="25.1"
   description="Altera LPDDR Nextgen Memory Controller"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controllers"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="ip_compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria V /// Cyclone V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_nextgen_lpddr_controller_core"
   file="alt_mem_if/alt_mem_if_controllers/alt_mem_if_nextgen_lpddr_controller_core/alt_mem_if_nextgen_lpddr_controller_core_hw.tcl"
   displayName="Altera LPDDR Nextgen Memory Controller Core"
   version="25.1"
   description="Altera LPDDR Nextgen Memory Controller Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Controller Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="ip_upgrade" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria V /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <plugin
   name="altera_mem_if_nios2_hal_driver"
   file="alt_mem_if/altera_mem_if_nios2_hal/altera_mem_if_nios2_hal_sw.tcl"
   displayName="altera_mem_if_nios2_hal_driver"
   version="24.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_mem_if_nios2"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_mem_if_oct"
   file="alt_mem_if/altera_mem_if_oct/altera_mem_if_oct_hw.tcl"
   displayName="External Memory OCT block"
   version="25.1"
   description="External Memory OCT block"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_oct_bridge"
   file="alt_mem_if/altera_mem_if_oct_bridge/altera_mem_if_oct_bridge_hw.tcl"
   displayName="External Memory OCT block bridge"
   version="25.1"
   description="External Memory OCT block bridge"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_pll_bridge"
   file="alt_mem_if/altera_mem_if_pll_bridge/altera_mem_if_pll_bridge_hw.tcl"
   displayName="External Memory PLL block bridge"
   version="25.1"
   description="External Memory PLL block bridge"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_pp_mem_model_bridge"
   file="alt_mem_if/ed_comps/altera_mem_if_pp_mem_model_bridge/altera_mem_if_pp_mem_model_bridge_hw.tcl"
   displayName="Altera Ping Pong PHY Memory Model Bridge"
   version="25.1"
   description="Altera Ping Pong PHY Memory Model Bridge"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_qdrii_afi_mux"
   file="alt_mem_if/altera_mem_if_afi_muxes/altera_mem_if_qdrii_afi_mux/altera_mem_if_qdrii_afi_mux_hw.tcl"
   displayName="Altera QDRII AFI Multiplexer"
   version="25.1"
   description="Altera QDRII AFI Multiplexer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory AFI Multiplexers"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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 <component
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   displayName="QDR II/II+ External Memory PLL/DLL/OCT block"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Example Design Components"
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  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_mem_if_rldramii_phy_core"
   file="alt_mem_if/alt_mem_if_phys/alt_mem_if_rldramii_phy_core/altera_mem_if_rldramii_phy_core_hw.tcl"
   displayName="RLDRAM II External Memory PHY"
   version="25.1"
   description="RLDRAM II External Memory PHY"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
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 </component>
 <component
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   file="alt_mem_if/altera_mem_if_pll/altera_mem_if_rldramii_pll/altera_mem_if_rldramii_pll_hw.tcl"
   displayName="RLDRAM II External Memory PLL/DLL/OCT block"
   version="25.1"
   description="RLDRAM II External Memory PLL/DLL/OCT block"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory PHYs"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
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 </component>
 <component
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencers"
   factory="TclModuleFactory">
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 <component
   name="altera_mem_if_rldramii_rseq"
   file="alt_mem_if/altera_mem_if_rseq/altera_mem_if_rldramii_rseq/altera_mem_if_rldramii_rseq_hw.tcl"
   displayName="RLDRAMII RTL Sequencer"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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 <component
   name="altera_mem_if_sequencer_cpu"
   file="alt_mem_if/altera_mem_if_sequencer_cpu/altera_mem_if_sequencer_cpu_hw.tcl"
   displayName="UniPHY Sequencer CPU"
   version="25.1"
   description="UniPHY Sequencer CPU"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
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 <component
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 <component
   name="altera_mem_if_sequencer_rst"
   file="alt_mem_if/altera_mem_if_qseq/altera_mem_if_sequencer_rst/altera_mem_if_sequencer_rst_hw.tcl"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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 </component>
 <component
   name="altera_mem_if_sideband_terminator"
   file="alt_mem_if/alt_mem_if_example_design_components/altera_mem_if_sideband_terminator/altera_mem_if_sideband_terminator_hw.tcl"
   displayName="UniPHY Controller Sideband Terminator"
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   description="UniPHY Controller Sideband Terminator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Example Design Components"
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 <component
   name="altera_mem_if_simple_avalon_mm_bridge"
   file="alt_mem_if/bridges/altera_mem_if_simple_avalon_mm_bridge/altera_mem_if_simple_avalon_mm_bridge_hw.tcl"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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 </component>
 <component
   name="altera_mem_if_single_clock_pll"
   file="alt_mem_if/ed_comps/altera_mem_if_single_clock_pll/altera_mem_if_single_clock_pll_hw.tcl"
   displayName="alt_mem_if Single Clock PLL"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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 <component
   name="altera_mem_if_temp_sense"
   file="alt_mem_if/ed_comps/temp_sensor_top/altera_mem_if_temp_sensor_hw.tcl"
   displayName="altera_mem_if Temperature Sensor"
   version="25.1"
   description="altera_mem_if Temperature Sensor"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Example Design Components"
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 <component
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   file="merlin/altera_merlin_ahb_slave_agent/altera_merlin_ahb_slave_agent_hw.tcl"
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 <component
   name="altera_merlin_apb_master_agent"
   file="merlin/altera_merlin_apb_master_agent/altera_merlin_apb_master_agent_hw.tcl"
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   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=apb,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=false"
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 <component
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 <component
   name="altera_merlin_axi_master_ni"
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 <component
   name="altera_merlin_axi_slave_ni"
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 </component>
 <component
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   file="merlin/altera_merlin_axi_translator/altera_merlin_axi_translator_hw.tcl"
   displayName="AXI Translator"
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  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_burst_adapter"
   file="merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl"
   displayName="Memory Mapped Burst Adapter"
   version="25.1"
   description="Accommodates the burst capabilities of each interface in the system, including interfaces that do not support burst transfers, translating burst sizes as required."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_combined_width_adapter"
   file="merlin/altera_merlin_combined_width_adapter/altera_merlin_combined_width_adapter_hw.tcl"
   displayName="Memory Mapped Combined Width Adapter"
   version="25.1"
   description="Combine command and response width adapter."
   tags="CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=false"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_conduit_fanout"
   file="altera_pcie/altera_pcie_avmm/altera_merlin_conduit_fanout_hw.tcl"
   displayName="Merlin Conduit Fanout"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Merlin Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_merlin_demultiplexer"
   file="merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl"
   displayName="Memory Mapped Demultiplexer"
   version="25.1"
   description="Accepts channelized data on its sink interface and transmits the data on one of its source interfaces."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_master_agent"
   file="merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl"
   displayName="Avalon MM Master Agent"
   version="25.1"
   description="Translates Avalon-MM master transactions into Qsys command packets and translates the Qsys Avalon-MM slave response packets into Avalon-MM responses. Refer to the Avalon Interface Specifications (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf) for an explanation of bursting behavior."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_master_translator"
   file="merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl"
   displayName="Avalon MM Master Translator"
   version="25.1"
   description="Converts the Avalon-MM master interface to a simpler representation that the Qsys network uses. Refer to the Avalon Interface Specifications (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf) for definitions of the Avalon-MM signals and explanations of the bursting properties."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_mins_network_generator"
   file="merlin/altera_merlin_mins_network_generator/altera_merlin_mins_network_generator_hw.tcl"
   displayName="Network Generator"
   version="25.1"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_merlin_multiplexer"
   file="merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl"
   displayName="Memory Mapped Multiplexer"
   version="25.1"
   description="Arbitrates between requesting masters using an equal share, round-robin algorithm. The arbitration scheme can be changed to weighted round-robin by specifying a relative number of arbitration shares to the masters that access a particular slave."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_multithread_traffic_limiter"
   file="merlin/altera_merlin_multithread_traffic_limiter/multithread_limiter/altera_merlin_multithread_traffic_limiter_hw.tcl"
   displayName="Memory-Mapped Multithread Traffic Limiter"
   version="25.1"
   description="Multiple Thread Traffic Limiter"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_network"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="com.altera.sopcmodel.transforms.avalon.placeholders.Network"
   version="25.1"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories=""
   factory="BeanElementFactory" />
 <component
   name="altera_merlin_router"
   file="merlin/altera_merlin_router/altera_merlin_router_hw.tcl"
   displayName="Memory Mapped Router"
   version="25.1"
   description="Routes command packets from the master to the slave and response packets from the slave to the master."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_sc_fifo_limiter"
   file="merlin/altera_merlin_multithread_traffic_limiter/sc_fifo_limiter/altera_merlin_sc_fifo_limiter_hw.tcl"
   displayName="Memory-Mapped Combined sc_fifo Limiter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_slave_agent"
   file="merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl"
   displayName="Avalon MM Slave Agent"
   version="25.1"
   description="Accepts command packets and issues the resulting transactions to the Avalon interface. Refer to the Avalon Interface Specifications (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf) for explanations of the bursting properties."
   tags="AUTHORSHIP=Altera Corporation"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_slave_translator"
   file="merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl"
   displayName="Avalon MM Slave Translator"
   version="25.1"
   description="Converts the Avalon-MM slave interface to a simplified representation that the Qsys network uses. Refer to the Avalon Interface Specifications (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf) for definitions of the Avalon-MM signals and explanations of the bursting properties and address alignment."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_st_pass_through"
   file="merlin/altera_merlin_mins_network_generator/altera_merlin_st_pass_through_hw.tcl"
   displayName="Pass Through"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Merlin Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_merlin_std_arbitrator"
   file="merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_hw.tcl"
   displayName="Memory Mapped Arbiter"
   version="25.1"
   description="Arbitrates between requesting masters using an equal share, round-robin algorithm. The arbitration scheme can be changed to weighted round-robin by specifying a relative number of arbitration shares to the masters that access a particular slave."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_threadid_mapping"
   file="merlin/altera_merlin_multithread_traffic_limiter/threadid_mapping/altera_merlin_threadid_mapping_hw.tcl"
   displayName="Memory-Mapped ThreadID mapping"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=false"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_merlin_threadid_splitter"
   file="merlin/altera_merlin_multithread_traffic_limiter/threadid_splitter/altera_merlin_threadid_splitter_hw.tcl"
   displayName="Memory-Mapped ThreadIDs Splitter"
   version="25.1"
   description="Multiple thread ID splitter"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
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   displayName="Memory Mapped Traffic Limiter"
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   description="Ensures the responses arrive in order, simplifying the Qsys response network."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset"
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   factory="TclModuleFactory">
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 <component
   name="altera_merlin_width_adapter"
   file="merlin/altera_merlin_width_adapter/altera_merlin_width_adapter_hw.tcl"
   displayName="Memory Mapped Width Adapter"
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   description="Converts between Avalon-MM master and slaves with different data and byte enable widths."
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   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
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   file="sld/core/altera_mgmt_reset/altera_mgmt_reset_hw.tcl"
   displayName="Altera Management Reset Block"
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   description="Translate management ST input to reset_n output"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
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 <component
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   file="sld/mm/altera_mm_debug_link/altera_mm_debug_link_hw.tcl"
   displayName="Avalon-MM Debug Link"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
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 <component
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   displayName="altera_mm_debug_link_addr_fixer"
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   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=true"
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 <component
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   displayName="altera_mm_debug_link_constant"
   version="25.1"
   description=""
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   categories=""
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 <component
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   description=""
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 <component
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   file="merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl"
   displayName="MM Interconnect"
   version="25.1"
   description="MM Interconnect"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Merlin Components"
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   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
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 <component
   name="altera_modular_adc"
   file="altera_modular_adc/top/altera_modular_adc_hw.tcl"
   displayName="Modular ADC core IP"
   version="25.1"
   description="Altera Modular ADC"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Peripherals"
   factory="TclModuleFactory">
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 <component
   name="altera_modular_adc_conduit_splitter"
   file="altera_modular_adc/conduit_splitter/altera_modular_adc_conduit_splitter_hw.tcl"
   displayName="Modular ADC command_in Splitter core Intel FPGA IP"
   version="25.1"
   description="Altera Modular ADC - conduit splitter core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Processors and Peripherals/Peripherals"
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 <component
   name="altera_modular_adc_control"
   file="altera_modular_adc/control/altera_modular_adc_control_hw.tcl"
   displayName="Modular ADC Control core Intel FPGA IP"
   version="25.1"
   description="Altera Modular ADC - Control core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
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 <plugin
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   file="altera_modular_adc/top/altera_modular_adc_sw.tcl"
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   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_modular_adc"
   categories="driver_element"
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   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
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 <component
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   file="altera_modular_adc/response_merge/altera_modular_adc_response_merge_hw.tcl"
   displayName="Modular ADC Response Merge core Intel FPGA IP"
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   description="Altera Modular ADC - Response Merge core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
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 <component
   name="altera_modular_adc_sample_store"
   file="altera_modular_adc/sample_store/altera_modular_adc_sample_store_hw.tcl"
   displayName="Modular ADC Sample Storage core Intel FPGA IP"
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   description="Altera Modular ADC - Sample Storage core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Processors and Peripherals/Peripherals"
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 <component
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   file="altera_modular_adc/sequencer/altera_modular_adc_sequencer_hw.tcl"
   displayName="Modular ADC Sequencer core Intel FPGA IP"
   version="25.1"
   description="Altera Modular ADC - Standard Sequencer core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Processors and Peripherals/Peripherals"
   factory="TclModuleFactory">
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 <component
   name="altera_modular_adc_threshold_detect"
   file="altera_modular_adc/threshold_detect/altera_modular_adc_threshold_detect_hw.tcl"
   displayName="Modular ADC Threshold Detect core Intel FPGA IP"
   version="25.1"
   description="Altera Modular ADC - Threshold Detection core"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Processors and Peripherals/Peripherals"
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 <component
   name="altera_modular_dual_adc"
   file="altera_modular_adc/top/altera_modular_adc_dual_hw.tcl"
   displayName="Modular Dual ADC core IP"
   version="25.1"
   description="Altera Modular Dual ADC"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Peripherals"
   factory="TclModuleFactory">
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 <plugin
   name="altera_modular_dual_adc_driver"
   file="altera_modular_adc/top/altera_modular_adc_dual_sw.tcl"
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   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_modular_dual_adc"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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 <component
   name="altera_msgdma"
   file="altera_msgdma/top/altera_msgdma_hw.tcl"
   displayName="Modular Scatter-Gather DMA IP"
   version="25.1"
   description="Modular SGDMA with configuration mode of Avalon-MM to Avalon-MM, Avalon-MM to Avalon-ST, or Avalon-ST to Avalon-MM data paths"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/DMA"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="do_validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/lro1402196946061" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <plugin
   name="altera_msgdma_driver"
   file="altera_msgdma/top/altera_msgdma_sw.tcl"
   displayName="altera_msgdma_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_msgdma"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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 <component
   name="altera_msgdma_prefetcher"
   file="altera_msgdma/prefetcher/altera_msgdma_prefetcher_hw.tcl"
   displayName="Modular SGDMA Prefetcher IP"
   version="25.1"
   description="SGDMA prefetching block"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock,interrupt /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/DMA/mSGDMA Sub-core"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate_me" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_me" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_msi_to_gic_gen"
   file="altera_msi_to_gic_gen/altera_msi_to_gic_gen_hw.tcl"
   displayName="MSI to GIC Generator IP"
   version="1.0"
   description="This component allow level interrupt generation to the host processor upon arrival of MSI(Message Signaled Interrupts)"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,interrupt,reset /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Inter-Process Communication"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/lro1403291922054" />
 </component>
 <component
   name="altera_mult_add"
   file="altera_mult_add/source/top/altera_mult_add_hw.tcl"
   displayName="Multiply Adder Intel FPGA IP"
   version="25.1"
   description="The ALTERA_MULT_ADD megafunction allows you to implement a multiplier-adder"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V /// Cyclone V /// Arria V GZ /// Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="User Guide For Stratix 10"
     type="OTHER"
     url="https://documentation.altera.com/#/link/kly1436148709581/kly1439175970736" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/ktw1517822281214.html" />
 </component>
 <component
   name="altera_nco_ii"
   file="dsp/altera_nco_ii/altera_nco_ii_hw.tcl"
   displayName="NCO"
   version="25.1"
   description="Altera Numerically Controlled Oscillator"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="DSP/Signal Generation"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix IV /// Stratix V /// Stratix 10 for Emulator Use /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// Cyclone IV GX /// Cyclone IV E /// Cyclone V /// Cyclone 10 LP /// MAX 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421694900164/hco1421694881684" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697884642" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="https://documentation.altera.com/#/link/hco1421694900164/hco1421694881684" />
 </component>
 <component
   name="altera_nios2_custom_instr_hybrid_master_bfm"
   file="sopc_builder_ip/verification/altera_nios2_custom_instr_hybrid_master_bfm/altera_nios2_custom_instr_hybrid_master_bfm_hw.tcl"
   displayName="Altera Nios II Custom Instruction Hybrid Master BFM"
   version="25.1"
   description="Altera Nios II Custom Instruction Hybrid Master BFM"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_nios2_custom_instr_master_bfm"
   file="sopc_builder_ip/verification/altera_nios2_custom_instr_master_bfm/altera_nios2_custom_instr_master_bfm_hw.tcl"
   displayName="Nios II Custom Instruction Master BFM Intel FPGA IP"
   version="25.1"
   description="Altera Nios II Custom Instruction Master BFM"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="none" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471592433" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_nios2_custom_instr_slave_bfm"
   file="sopc_builder_ip/verification/altera_nios2_custom_instr_slave_bfm/altera_nios2_custom_instr_slave_bfm_hw.tcl"
   displayName="Nios II Custom Instruction Slave BFM Intel FPGA IP"
   version="25.1"
   description="Altera Nios II Custom Instruction Slave BFM"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="none" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471592433" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1416836145555/hco1416836653221" />
 </component>
 <component
   name="altera_nios2_tmr_comparator"
   file="altera_nios2_tmr_comparator/altera_nios2_tmr_comparator_hw.tcl"
   displayName="Altera Nios II TMR Module"
   version="25.1"
   description=""
   tags="AUTHORSHIP= /// CONNECTION_TYPES=clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="altera_nios_custom_instr_bitswap"
   file="sopc_builder_ip/altera_nios_custom_instr_bitswap_qsys/bitswap_qsys_hw.tcl"
   displayName="Bitswap"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=nios_custom_instruction /// INTERNAL_COMPONENT=false"
   categories="Custom Instruction Modules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/hb/nios2/n2cpu_nii51006.pdf" />
 </component>
 <component
   name="altera_nios_custom_instr_endian_converter"
   file="sopc_builder_ip/altera_nios_custom_instr_endian_converter_qsys/converter_qsys_hw.tcl"
   displayName="Endian Converter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=nios_custom_instruction /// INTERNAL_COMPONENT=true"
   categories="Custom Instruction Modules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="altera_nios_custom_instr_floating_point"
   file="sopc_builder_ip/altera_nios_custom_instr_floating_point_qsys/fpoint_qsys_hw.tcl"
   displayName="Floating Point Hardware"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=nios_custom_instruction /// INTERNAL_COMPONENT=false"
   categories="Custom Instruction Modules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_nios_custom_instr_floating_point_2"
   file="altera_nios_custom_instr_floating_point_2/altera_nios_custom_instr_floating_point_2/fpoint2_qsys_hw.tcl"
   displayName="Floating Point Hardware 2"
   version="25.1"
   description="&lt;html&gt; This component is the 2nd generation set of single-precision floating-point custom instructions.&lt;br&gt; It offers improved performance and lower resource usage than the 1st generation at the&lt;br&gt; expense of full IEEE 754 compliance (limited subnormal support and simplified rounding modes).&lt;br&gt; &lt;/html&gt;"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Co-Processors/Nios II Custom Instructions"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="Data Sheet "
     type="OTHER"
     url="http://www.altera.com/content/dam/altera-www/global/en_US/others/literature/ug/ug_fph2.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lro1431971056906/lro1432313552838" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697867298" />
 </component>
 <component
   name="altera_nios_custom_instr_floating_point_2_combi"
   file="altera_nios_custom_instr_floating_point_2/altera_nios_custom_instr_floating_point_2_combi/fpoint2_combi_qsys_hw.tcl"
   displayName="Floating Point Hardware 2 Combinatorial"
   version="25.1"
   description="This component represents part of the Floating Point Hardware 2 where the Arithmetic and Comparison operations are performed"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=nios_custom_instruction /// INTERNAL_COMPONENT=false"
   categories="DSP/Floating Point"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="Data Sheet "
     type="OTHER"
     url="http://www.altera.com/content/dam/altera-www/global/en_US/others/literature/ug/ug_fph2.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lro1431971056906/lro1432313552838" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697867298" />
 </component>
 <component
   name="altera_nios_custom_instr_floating_point_2_multi"
   file="altera_nios_custom_instr_floating_point_2/altera_nios_custom_instr_floating_point_2_multi/fpoint2_multi_qsys_hw.tcl"
   displayName="Floating Point Hardware 2 Multi-cycle"
   version="25.1"
   description="This component represents part of the Floating Point Hardware 2 where the Arithmetic, Root and Conversion operations are performed"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=nios_custom_instruction /// INTERNAL_COMPONENT=false"
   categories="DSP/Floating Point"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="Data Sheet "
     type="OTHER"
     url="http://www.altera.com/content/dam/altera-www/global/en_US/others/literature/ug/ug_fph2.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lro1431971056906/lro1432313552838" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697867298" />
 </component>
 <component
   name="altera_nios_custom_instr_interrupt_vector"
   file="sopc_builder_ip/altera_nios_custom_instr_interrupt_vector_qsys/interrupt_vector_qsys_hw.tcl"
   displayName="Interrupt Vector"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=nios_custom_instruction /// INTERNAL_COMPONENT=true"
   categories="Custom Instruction Modules"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="altera_ocp_fabric"
   file="sld/core/altera_ocp_fabric/altera_ocp_fabric_hw.tcl"
   displayName="OpenCore Plus Fabric"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_oct"
   file="altera_oct/altera_oct_top/altera_oct_hw.tcl"
   displayName="OCT Intel FPGA IP"
   version="25.1"
   description="OCT Intel FPGA IP"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/I/O"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="parameter_upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="Altera OCT user guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_altera_oct.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sam1412662517164/sam1412662458255" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_oct_core14"
   file="altera_oct/altera_oct_core14/altera_oct_hw.tcl"
   displayName="Altera OCT Core"
   version="25.1"
   description="Altera OCT Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="I/O"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,QUARTUS_SYNTH,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_oct_core20"
   file="altera_oct/altera_oct_core20/altera_oct_hw.tcl"
   displayName="Altera OCT Core"
   version="25.1"
   description="Altera OCT Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="I/O"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,QUARTUS_SYNTH,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_oct_driver"
   file="altera_oct/altera_oct_driver/altera_oct_driver_hw.tcl"
   displayName="Altera OCT Driver"
   version="25.1"
   description="Altera OCT Driver"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="I/O"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_onchip_flash"
   file="altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_hw.tcl"
   displayName="On-Chip Flash IP"
   version="25.1"
   description="On-Chip Flash Megafunction with Avalon-MM Slave Interface."
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="parameter_upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="MAX 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683180/current/user-flash-memory-overview.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683180/current/document-revision-history-for-the-user.html" />
 </component>
 <plugin
   name="altera_onchip_flash_driver"
   file="altera_onchip_flash/altera_onchip_flash/altera_onchip_flash_sw.tcl"
   displayName="altera_onchip_flash_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_onchip_flash"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_parallel_flash_loader"
   file="altera_parallel_flash_loader/altera_parallel_flash_loader_hw.tcl"
   displayName="Parallel Flash Loader IP"
   version="25.1"
   description="The Parallel Flash Loader IP megafunction provides an in-system JTAG  programming method for Common Flash Interface (CFI) flash, quad Serial  Peripheral Interface(SPI) flash, or NAND flash memory devices, and allow  FPGA configuration from the flash memory devices."
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Cyclone 10 LP /// Cyclone IV E /// Cyclone IV GX /// Cyclone V /// MAX 10 /// MAX II /// MAX V /// Stratix IV /// Stratix V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html" />
 </component>
 <component
   name="altera_parallel_flash_loader_2"
   file="pgm/altera_parallel_flash_loader_2/altera_parallel_flash_loader_2/altera_parallel_flash_loader_2_hw.tcl"
   displayName="Parallel Flash Loader II IP"
   version="25.1"
   description="The Parallel Flash Loader II IP megafunction provides an in-system JTAG programming method for Common Flash Interface FPGA configuration from the flash memory devices. You can use the Parallel Flash Loader II IP with an external host, such as the MAX II, MAX V, or MAX 10 devices to complete the following tasks: Program configuration data into a flash memory device using JTAG interface; Configure the Stratix 10 device with the Avalon -ST configuration scheme from the flash memory device."
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Cyclone 10 LP /// Cyclone IV E /// Cyclone IV GX /// Cyclone V /// MAX 10 /// MAX II /// MAX V /// Stratix IV /// Stratix V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide (Stratix 10)"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683762/current/ip-for-use-with-the-st-configuration.html" />
  <documentUrl
     displayName="User Guide (Agilex 7)"
     type="OTHER"
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  <documentUrl
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  <documentUrl
     displayName="Release Notes "
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/683318/" />
 </component>
 <component
   name="altera_pcie_256_hip_avmm"
   file="altera_pcie/altera_pcie_hip_256_avmm/altera_pcie_256_hip_avmm_hw.tcl"
   displayName="V-Series Avalon-MM DMA for PCI Express Intel FPGA IP"
   version="25.1"
   description="V-Series Avalon-MM DMA for PCI Express"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V /// Cyclone V /// Arria V GZ" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="Application Note"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412548086590/nik1412548063092" />
  <documentUrl
     displayName="Application note"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412473924913/nik1412473905263" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1410905927419/nik1410905278518" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698001659" />
 </component>
 <component
   name="altera_pcie_a10_ed"
   file="altera_pcie/altera_pcie_a10_ed/altera_pcie_a10_ed_hw.tcl"
   displayName="Example : Intel Arria 10 Application for Avalon-Streaming Hard IP for PCI Express"
   version="25.1"
   description="Example : Intel Arria 10 Application for Avalon-Streaming hard IP for PCI Express"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express/QSYS Example Designs"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="User guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_a10_pcie.pdf" />
  <documentUrl
     displayName="Release Notes:"
     type="OTHER"
     url="http://www.altera.com/literature/rn/ip/#other_ip.html" />
  <documentUrl
     displayName="Application Note"
     type="OTHER"
     url="http://www.altera.com/literature/an/an690.pdf" />
  <documentUrl
     displayName="Application note"
     type="OTHER"
     url="http://www.altera.com/literature/an/an456.pdf" />
  <documentUrl
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697736501" />
 </component>
 <component
   name="altera_pcie_a10_hip"
   file="altera_pcie/altera_pcie_a10_hip/altera_pcie_a10_hip_hw.tcl"
   displayName="Intel Arria 10/Cyclone 10 Hard IP for PCI Express"
   version="25.1"
   description="Intel Arria 10/Cyclone 10 Hard IP for PCI Express"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_pcie_a10_hip::module::elaborate" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_pcie_a10_hip::parameters::upgrade" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
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     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Arria 10 Avalon-ST Interface for PCIe Solutions User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1414599283601/nik1410905278518" />
  <documentUrl
     displayName="Arria 10 Avalon-ST Hard IP for PCI Express Design Example User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/owv1467062573484/lbl1441208916409" />
  <documentUrl
     displayName="Arria 10 Avalon-MM Interface for PCIe Solutions User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1415230609011/nik1410905278518" />
  <documentUrl
     displayName="Arria 10 Avalon-MM  Hard IP for PCI Express Design Example User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/xtq1467072880606/lbl1441208916409" />
  <documentUrl
     displayName="Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1415138844137/nik1410905278518" />
  <documentUrl
     displayName="Getting Started with the Avalon-MM DMA Design Example"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1415138844137/nik1410905310368" />
  <documentUrl
     displayName="Arria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1415123763821/nik1410905278518" />
  <documentUrl
     displayName="Getting Started with the SR-IOV Design Example"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1415123763821/lbl1443202387473" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697756668" />
 </component>
 <component
   name="altera_pcie_a10_tbed"
   file="altera_pcie/altera_pcie_a10_tbed/altera_pcie_a10_tbed_hw.tcl"
   displayName="Testbench for Avalon-Streaming Arria 10 hard IP for PCI Express"
   version="25.1"
   description="Testbench for Avalon-Streaming Arria 10 hard IP for PCI Express"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_s5_pcie.pdf" />
  <documentUrl
     displayName="User guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_a10_pcie.pdf" />
  <documentUrl
     displayName="Release Notes:"
     type="OTHER"
     url="http://www.altera.com/literature/rn/ip/#other_ip.html" />
  <documentUrl
     displayName="Application Note"
     type="OTHER"
     url="http://www.altera.com/literature/an/an690.pdf" />
  <documentUrl
     displayName="Application note"
     type="OTHER"
     url="http://www.altera.com/literature/an/an456.pdf" />
 </component>
 <component
   name="altera_pcie_av_hip_ast"
   file="altera_pcie/altera_pcie_av_hip_ast/altera_pcie_av_hip_ast_hw.tcl"
   displayName="Arria V Hard IP for PCI Express"
   version="25.1"
   description="Arria V Hard IP for PCI Express"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="false" />
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  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria V" />
  <tag2
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  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
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     url="https://documentation.altera.com/#/link/nik1412548086590/nik1412548063092" />
  <documentUrl
     displayName="Application note"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412473924913/nik1412473905263" />
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     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1415574515926/nik1410564766721" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697736501" />
 </component>
 <component
   name="altera_pcie_av_hip_avmm"
   file="altera_pcie/altera_pcie_av_hip_avmm/altera_pcie_av_hip_avmm_hw.tcl"
   displayName="Avalon-MM Arria V Hard IP for PCI Express"
   version="25.1"
   description="Avalon-MM Arria V Hard IP for PCI Express"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express"
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697736501" />
 </component>
 <component
   name="altera_pcie_avgz_hip_ast"
   file="altera_pcie/altera_pcie_avgz_hip_ast/altera_pcie_avgz_hip_ast_hw.tcl"
   displayName="Arria V GZ Hard IP for PCI Express"
   version="25.1"
   description="Arria V GZ Hard IP for PCI Express"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
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  <documentUrl
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     type="OTHER"
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 </component>
 <component
   name="altera_pcie_avgz_hip_avmm"
   file="altera_pcie/altera_pcie_avgz_hip_avmm/altera_pcie_avgz_hip_avmm_hw.tcl"
   displayName="Avalon-MM Arria V GZ Hard IP for PCI Express"
   version="25.1"
   description="Avalon-MM Arria V GZ Hard IP for PCI Express"
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     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1415317521608/nik1410905278518" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697731237" />
 </component>
 <component
   name="altera_pcie_bfm"
   file="altera_pcie/altera_pcie_avmm/altera_pcie_bfm_hw.tcl"
   displayName="altera_pcie_bfm"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_pcie_bfm_qsys"
   file="altera_pcie/altera_pcie_avmm/altera_pcie_bfm_qsys_hw.tcl"
   displayName="altera_pcie_bfm_qsys"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix IV /// Cyclone IV GX" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="altera_pcie_cfgbp_ed"
   file="altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/altera_pcie_cfgbp_ed_hw.tcl"
   displayName="Example : Config-Bypass App Example"
   version="25.1"
   description="Config-Bypass Application Example Design for PCI Express"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express/QSYS Example Designs"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V GZ /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_s5_pcie.pdf" />
 </component>
 <component
   name="altera_pcie_channelizer"
   file="altera_pcie/altera_pcie_hip_256_avmm/channelizer/channelizer_hw.tcl"
   displayName="PCI Express Multi-Channel DMA Interface"
   version="25.1"
   description="PCI Express Channelizer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express/QSYS Example Designs"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="User guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug_s5_pcie_avmm_dma.pdf" />
  <documentUrl
     displayName="Release Notes:"
     type="OTHER"
     url="http://www.altera.com/literature/rn/ip/#pcie_channelizer_revision.html" />
 </component>
 <component
   name="altera_pcie_channelizer"
   file="altera_pcie/altera_pcie_hip_256_avmm/channelizer/PCIe_Channelizer_hw.tcl"
   displayName="PCI Express Multi-Channel DMA Interface"
   version="25.1"
   description="PCI Express Channelizer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express/QSYS Example Designs"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="User guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug_s5_pcie_avmm_dma.pdf" />
  <documentUrl
     displayName="Release Notes:"
     type="OTHER"
     url="http://www.altera.com/literature/rn/ip/#pcie_channelizer_revision.html" />
 </component>
 <component
   name="altera_pcie_conduit_fanout"
   file="altera_pcie/altera_pcie_avmm/altera_pcie_conduit_fanout_hw.tcl"
   displayName="altera_pcie_conduit_fanout"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix IV" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation" />
 </component>
 <component
   name="altera_pcie_cv_hip_ast"
   file="altera_pcie/altera_pcie_cv_hip_ast/altera_pcie_cv_hip_ast_hw.tcl"
   displayName="Cyclone V Hard IP for PCI Express"
   version="25.1"
   description="Cyclone V Hard IP for PCI Express"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Cyclone V" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="Application Note"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412548086590/nik1412548063092" />
  <documentUrl
     displayName="Application note"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412473924913/nik1412473905263" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1415752160039/nik1410564766721" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697792335" />
 </component>
 <component
   name="altera_pcie_cv_hip_avmm"
   file="altera_pcie/altera_pcie_cv_hip_avmm/altera_pcie_cv_hip_avmm_hw.tcl"
   displayName="Avalon-MM Cyclone V Hard IP for PCI Express"
   version="25.1"
   description="Avalon-MM Cyclone V Hard IP for PCI Express"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Cyclone V" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="Application Note"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412548086590/nik1412548063092" />
  <documentUrl
     displayName="Application note"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412473924913/nik1412473905263" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1415574081617/nik1410905278518" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697792335" />
 </component>
 <component
   name="altera_pcie_descriptor_controller"
   file="altera_pcie/altera_pcie_hip_256_avmm/control/altera_pcie_desc_control_hw.tcl"
   displayName="Example : Altera PCIe Descriptor Controller"
   version="1.0"
   description="Manages the DMA reads and writes operations on the &apos;Avalon-MM 256-bit Hard IP for PCI Express&apos; (not compatible with other DMAs)"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express/QSYS Example Designs"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V /// Cyclone V /// Arria V GZ" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_s5_pcie.pdf" />
 </component>
 <component
   name="altera_pcie_dma_fifo_mode"
   file="altera_pcie/altera_pcie_hip_256_avmm/fifo_mode/altera_pcie_dma_fifo_mode_hw.tcl"
   displayName="Avalon-MM DMA FIFO Mode IP Core for PCI Express"
   version="25.1"
   description="Avalon-MM DMA FIFO Mode IP Core for PCI Express"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express/QSYS Example Designs"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V /// Cyclone V /// Arria V GZ /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="Avalon-MM DMA FIFO"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_dma_fifo.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/lbl1411591294497/lbl1411591409707" />
 </component>
 <component
   name="altera_pcie_hard_ip"
   file="altera_pcie/altera_pcie_avmm/altera_pcie_hard_ip_hw.tcl"
   displayName="IP_Compiler for PCI Express"
   version="25.1"
   description="IP_Compiler for PCI Express"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix IV /// Arria II GX /// Arria II GZ /// Cyclone IV GX" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="https://www.altera.com/products/intellectual-property/all-ip/interface-protocols/m-alt-pcie8.html" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/en_US/pdfs/literature/ug/ug_pci_express.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697836712" />
 </component>
 <component
   name="altera_pcie_hip_ast_ed"
   file="altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_hip_ast_ed_hw.tcl"
   displayName="Example : Application Avalon-Streaming Hard IP for PCI Express"
   version="25.1"
   description="Example : Application for Avalon-Streaming hard IP for PCI Express"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express/Example Design Components"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V /// Cyclone V /// Arria V GZ" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_s5_pcie.pdf" />
  <documentUrl
     displayName="User guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_s5_pcie.pdf" />
  <documentUrl
     displayName="Release Notes:"
     type="OTHER"
     url="http://www.altera.com/literature/rn/ip/#other_ip.html" />
  <documentUrl
     displayName="Application note:"
     type="OTHER"
     url="http://www.altera.com/literature/an/an456.pdf" />
 </component>
 <component
   name="altera_pcie_internal_altgx"
   file="altera_pcie/altera_pcie_avmm/altera_pcie_internal_altgx_hw.tcl"
   displayName="altera_pcie_internal_altgx"
   version="25.1"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="GENERATION_CALLBACK" value="my_generation_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix IV /// Arria II GX /// Arria II GZ /// Cyclone IV GX" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <tag2 key="VALIDATION_CALLBACK" value="my_validation_callback" />
 </component>
 <component
   name="altera_pcie_internal_hard_ip"
   file="altera_pcie/altera_pcie_avmm/altera_pcie_internal_hard_ip_hw.tcl"
   displayName="Altera PCIe Internal Hard IP"
   version="25.1"
   description="Altera PCIe Internal Hard IP"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix IV" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="https://www.altera.com/products/intellectual-property/all-ip/interface-protocols/m-alt-pcie8.html" />
 </component>
 <component
   name="altera_pcie_internal_hard_ip_qsys"
   file="altera_pcie/altera_pcie_avmm/altera_pcie_internal_hard_ip_qsys_hw.tcl"
   displayName="Altera PCIe Internal Hard IP QSYS"
   version="25.1"
   description="Altera PCIe Internal Hard IP QSYS"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix IV /// Arria II GX /// Arria II GZ /// Cyclone IV GX" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="https://www.altera.com/products/intellectual-property/all-ip/interface-protocols/m-alt-pcie8.html" />
 </component>
 <component
   name="altera_pcie_internal_pipe_interface"
   file="altera_pcie/altera_pcie_avmm/altera_pcie_internal_pipe_interface_hw.tcl"
   displayName="altera_pcie_internal_pipe_interface"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix IV" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
 </component>
 <component
   name="altera_pcie_internal_pipe_interface_qsys"
   file="altera_pcie/altera_pcie_avmm/altera_pcie_internal_pipe_interface_qsys_hw.tcl"
   displayName="altera_pcie_internal_pipe_interface_qsys"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
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   displayName="Example : PCIe SR-IOV AVMM DMA Router"
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 <component
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   file="altera_pcie/altera_pcie_target_sriov_ed/altera_pcie_sriov_target_app_hw.tcl"
   displayName="Example Design : Target app for PCIe SR-IOV"
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 </component>
 <component
   name="altera_pcie_tbed"
   file="altera_pcie/altera_pcie_hip_ast_tbed/altera_pcie_tbed_sv_hw.tcl"
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  <documentUrl
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 </component>
 <component
   name="altera_pfl2_data_format_adapter"
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   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
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  <documentUrl
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     type="OTHER"
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 </component>
 <component
   name="altera_phylite"
   file="altera_phylite/hwtcl/altera_phylite/altera_phylite_hw.tcl"
   displayName="PHY Lite for Parallel Interfaces Arria 10 IP"
   version="25.1"
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 <component
   name="altera_phylite_addr_cmd"
   file="altera_phylite/ip_addr_cmd/altera_phylite_addr_cmd_hw.tcl"
   displayName="Address &amp; Command Logic for PHYLite Example Design"
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   description="PHYLite Address &amp; Command Logic for Example Design"
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   categories="Memories and Memory Controllers/External Memory Interfaces (Series 10)/Internal Components/altera_emif"
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 </component>
 <component
   name="altera_phylite_agent"
   file="altera_phylite/ip_agent/altera_phylite_agent_hw.tcl"
   displayName="Agent Memory Logic for PHYLite Example Design"
   version="25.1"
   description="PHYLite Memory Agent for Example Design"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memories and Memory Controllers/External Memory Interfaces (Series 10)/Internal Components/altera_emif"
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  <tag2
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  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altera_phylite.pdf" />
 </component>
 <component
   name="altera_phylite_arch_nd"
   file="altera_phylite/ip_arch_nd/altera_phylite_arch_nd_hw.tcl"
   displayName="PHYLite Core Component for 14nm Families"
   version="25.1"
   description="Altera PHYLite Core Component for 14nm Families"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memories and Memory Controllers/External Memory Interfaces (Series 10)/Internal Components/altera_emif"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_phylite::ip_arch_nd::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altera_phylite.pdf" />
 </component>
 <component
   name="altera_phylite_arch_nf"
   file="altera_phylite/ip_arch_nf/altera_phylite_arch_nf_hw.tcl"
   displayName="PHYLite Core Component for 20nm Families"
   version="25.1"
   description="Altera PHYLite Core Component for 20nm Families"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memories and Memory Controllers/External Memory Interfaces (Series 10)/Internal Components/altera_emif"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_phylite::ip_arch_nf::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altera_phylite.pdf" />
 </component>
 <component
   name="altera_phylite_avl_ctrl"
   file="altera_phylite/ip_avl_ctrl/altera_phylite_avl_ctrl_hw.tcl"
   displayName="Avalon Control Logic for Altera PHYLite Example Design"
   version="25.1"
   description="Altera PHYLite Avalon Control Logic for Example Design"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memories and Memory Controllers/External Memory Interfaces (Series 10)/Internal Components/altera_emif"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_phylite::ip_avl_ctrl::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altera_phylite.pdf" />
 </component>
 <component
   name="altera_phylite_cfg_ctrl"
   file="altera_phylite/ip_cfg_ctrl/altera_phylite_cfg_ctrl_hw.tcl"
   displayName="Dynamic Reconfiguration  Control Logic for Altera PHYLite Example Design"
   version="25.1"
   description="Altera PHYLite Dynamic Reconfiguration Control Logic for Example Design"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memories and Memory Controllers/External Memory Interfaces (Series 10)/Internal Components/altera_emif"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_phylite::ip_cfg_ctrl::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altera_phylite.pdf" />
 </component>
 <component
   name="altera_phylite_driver"
   file="altera_phylite/ip_driver/altera_phylite_driver_hw.tcl"
   displayName="Driver Core Logic for PHYLite Example Design"
   version="25.1"
   description="PHYLite Core Driver Logic for Example Design"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memories and Memory Controllers/External Memory Interfaces (Series 10)/Internal Components/altera_emif"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_phylite::ip_driver::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altera_phylite.pdf" />
 </component>
 <component
   name="altera_phylite_s10"
   file="altera_phylite/hwtcl/altera_phylite_s10/altera_phylite_s10_hw.tcl"
   displayName="PHY Lite for Parallel Interfaces Arria 10 IP"
   version="25.1"
   description="PHY Lite for Parallel Interfaces Arria 10 IP"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/I/O"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="COMPOSITION_CALLBACK"
     value="::altera_phylite::ip_top::main::composition_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_phylite::ip_top::main::parameter_upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="SUPPRESS_WARNINGS" value="NO_PORTS_AFTER_ELABORATION" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altera_phylite.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/" />
 </component>
 <component
   name="altera_phylite_sim_ctrl"
   file="altera_phylite/ip_sim_ctrl/altera_phylite_sim_ctrl_hw.tcl"
   displayName="Simulation Control Logic for PHYLite Example Design"
   version="25.1"
   description="PHYLite Simulation Control Logic for Example Design"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memories and Memory Controllers/External Memory Interfaces (Series 10)/Internal Components/altera_emif"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_phylite::ip_sim_ctrl::main::elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria 10 /// Stratix 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altera_phylite.pdf" />
 </component>
 <component
   name="altera_pll"
   file="altera_pll/source/top/pll_hw.tcl"
   displayName="PLL Intel FPGA IP"
   version="25.1"
   description="Intel Phase-Locked Loop"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Clocks; PLLs and Resets/PLL"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="my_parameter_upgrade" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V /// Arria V GZ /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/altera_pll.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mcn1401782837027/mcn1401784468028" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_pll_reconfig"
   file="altera_pll_reconfig/pll_reconfig_hw.tcl"
   displayName="PLL Reconfig IP"
   version="25.1"
   description="Phase-Locked Loop Reconfiguration Block"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Clocks; PLLs and Resets/PLL"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria V /// Arria V GZ /// Cyclone V /// Stratix V /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="Appnote"
     type="OTHER"
     url="http://www.altera.com/literature/an/an661.pdf" />
  <documentUrl displayName="DATASHEET" type="DATASHEET" url="" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mcn1424769382940/mcn1424770033682" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_qdrii_board_delay_model"
   file="alt_mem_if/ed_comps/board_delay_models/altera_qdrii_board_delay_model/altera_qdrii_board_delay_model_hw.tcl"
   displayName="Altera QDR II/II+ Board Delay Model"
   version="25.1"
   description="Altera QDR II/II+ Board Delay Model"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Board Delay Models"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="altera_qspi_address_adaption"
   file="pgm/altera_epcq_controller2/altera_qspi_address_adaption_hw.tcl"
   displayName="Serial Flash controller Address Adaption II IP"
   version="25.1"
   description="This component is a serial flash controller which allows user to access Altera EPCQ devices"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_remote_update"
   file="altera_remote_update/altera_remote_update_hw.tcl"
   displayName="Remote Update IP"
   version="25.1"
   description="The Remote Update megafunction provides features to download a new configuration image  from remote location, store in configuration device, and direct the dedicated remote system  upgrade circuitry to reconfigure itself with new configuration data."
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Stratix IV /// Stratix V /// Cyclone 10 LP" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/sam1412657373811.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/ign1517557574238.html" />
 </component>
 <component
   name="altera_remote_update_core"
   file="altera_remote_update/altera_remote_update_core_hw.tcl"
   displayName="Remote Update Core IP"
   version="25.1"
   description="The Remote Update megafunction provides features to download a new configuration image  from remote location, store in configuration device, and direct the dedicated remote system  upgrade circuitry to reconfigure itself with new configuration data."
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria 10 /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Stratix IV /// Stratix V /// Cyclone 10 LP" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_altremote.pdf?GSA_pos=5&amp;WT.oss_r=1&amp;WT.oss=remote update" />
 </component>
 <plugin
   name="altera_remote_update_driver"
   file="altera_remote_update/altera_remote_update_sw.tcl"
   displayName="altera_remote_update_driver"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_remote_update"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_reset_bridge"
   file="merlin/altera_reset_bridge/altera_reset_bridge_hw.tcl"
   displayName="Reset Bridge"
   version="25.1"
   description="Allows you to use a reset signal in two or more subsystems of your Qsys system. You can connect one reset source to the local components and export one or more to other subsystems as required."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset"
   categories="Basic Functions/Bridges and Adaptors/Reset"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_reset_controller"
   file="merlin/altera_reset_controller/altera_reset_controller_hw.tcl"
   displayName="Merlin Reset Controller"
   version="25.1"
   description="For systems with multiple reset inputs, the Merlin Reset Controller ORs all reset inputs and generates a single reset output."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset"
   categories="Basic Functions/Clocks; PLLs and Resets"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_reset_sequencer"
   file="merlin/altera_reset_sequencer/altera_reset_sequencer_hw.tcl"
   displayName="Reset Sequencer"
   version="25.1"
   description="Based on the input reset, controls the reset assertion and de-assertion sequence based on component parameterization"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset"
   categories="Basic Functions/Clocks; PLLs and Resets"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_reset_translator"
   file="merlin/altera_reset_translator/altera_reset_translator_hw.tcl"
   displayName="Reset Translator"
   version="25.1"
   description="Allows user to connect up non-matching reset interface by terminating unused ports"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset"
   categories="Qsys Interconnect/Memory-Mapped"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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   factory="TclModuleFactory">
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 <component
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   displayName="Altera RLDRAM3 Board Delay Model Bridge"
   version="25.1"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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 <component
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   file="rs_ii/src/rs_ucores/dec/altera_rs_ser_bm/altera_rs_ser_bm_hw.tcl"
   displayName="RS Serial Berlekamp-Massey"
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   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
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 <component
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   displayName="RS Serial Corrector"
   version="25.1"
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   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
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   version="25.1"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="DSP/Reed Solomon II"
   factory="TclModuleFactory">
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 <component
   name="altera_rs_ser_enc"
   file="rs_ii/src/enc/altera_rs_ser_enc/altera_rs_ser_enc_hw.tcl"
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   version="25.1"
   description="Altera Reed Solomon II Serial Encoder"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Reed Solomon II"
   factory="TclModuleFactory">
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 <component
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   file="rs_ii/src/rs_ucores/dec/altera_rs_ser_search/altera_rs_ser_search_hw.tcl"
   displayName="RS Serial Error Search"
   version="25.1"
   description="Altera Reed Solomon Search"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
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 <component
   name="altera_rs_ser_syn"
   file="rs_ii/src/rs_ucores/dec/altera_rs_ser_syn/altera_rs_ser_syn_hw.tcl"
   displayName="RS Serial Syndrome Generator"
   version="25.1"
   description="Altera Reed Solomon Serial Syndrome Generator"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
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 <component
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   file="rs_ii/src/rs_ucores/dec/altera_rs_ser_transaction_converter/altera_rs_ser_transaction_converter_hw.tcl"
   displayName="RS Serial Transaction Converter"
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   description="Altera Reed Solomon Serial Transaction Converter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
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 <component
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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 <component
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   description=""
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   file="native_mac/s10/fourteennm_mac_native_hw.tcl"
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   description="The NATIVE_DSP megafunction allows you to implement the primitive variable precision DSP block"
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 <component
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   file="dsp/altera_fpdsp_block/S10/S10FPDSP_hw.tcl"
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="DSP/Primitive DSP"
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 <component
   name="altera_sdram_partner_module"
   file="alt_mem_if/alt_mem_if_mem_models/altera_sdram_partner_module/sdram_partner_module_hw.tcl"
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   description="SDRAM Simulation Memory Model"
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 <component
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   displayName="Altera SDRAM Controller"
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   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
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 <component
   name="altera_serial_flash_loader"
   file="altera_serial_flash_loader/altera_serial_flash_loader_hw.tcl"
   displayName="Serial Flash Loader IP"
   version="25.1"
   description="The Serial Flash Loader IP megafunction provides a bridge that allows  in-system JTAG programming method for serial configuration devices."
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 <component
   name="altera_signaltap_agent"
   file="sld/jtag/altera_signaltap_agent/altera_signaltap_agent_hw.tcl"
   displayName="Altera SignalTap II Agent"
   version="25.1"
   description="Altera Signal Tap Agent"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
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 <component
   name="altera_signaltap_ii_logic_analyzer"
   file="sld/jtag/altera_signaltap_ii_logic_analyzer/altera_signaltap_ii_logic_analyzer_hw.tcl"
   displayName="Altera SignalTap II Logic Analyzer"
   version="25.1"
   description="Altera Signal Tap Logic Analyzer"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
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     value="HardCopy II /// APEX20K /// Cyclone V /// MAX9000 /// HardCopy III /// HardCopy IV /// Cyclone 10 LP /// EPC1 /// EPC2 /// eFPGA 28 HPM /// Programmer Dummy Family /// Cyclone IV E /// MAX V /// FLEX6000 /// Arria 10 /// Cyclone III LS /// FLEX10KE /// Soc Series V /// Stratix 10 for Emulator Use /// Arria II GX /// APEX II /// Arria II GZ /// Cyclone II /// FLEX10KB /// FLEX10KA /// Stratix /// MAX7000AE /// Stratix GX /// Cyclone III /// MAX3000A /// ALTERA /// Cyclone IV GX /// Enhanced Configuration Devices /// MAX 10 /// HardCopy Stratix /// MAX II /// Stratix III /// Arria V GZ /// MAX7000S /// Virtual JTAG TAP /// EMBEDDED_PROCESSOR /// ASC devices /// Cyclone /// Stratix II /// Stratix 10 /// FLEX10K /// FLEX8000 /// EXCALIBUR_ARM /// Stratix V /// MAX7000B /// MAX7000A /// ACEX1K /// APEX20KC /// Stratix II GX /// APEX20KE /// Arria GX /// Flash Memory /// Arria V /// None /// Mercury /// Stratix IV" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="Design Debugging Using the Signal Tap Logic Analyzer"
     type="OTHER"
     url="http://www.altera.com/literature/hb/qts/qts_qii53009.pdf" />
  <documentUrl
     displayName="sld_signaltap Megafunction Online Help"
     type="OTHER"
     url="http://quartushelp.altera.com/14.0/mergedProjects/hdl/mega/mega_file_sld_signaltap.htm?GSA_pos=43&amp;WT.oss_r=1&amp;WT.oss=signaltap" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1410385117325/mwh1410384469524" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_sl3"
   file="altera_sl3/src/top/altera_sl3_hw.tcl"
   displayName="SerialLite III Streaming"
   version="25.1"
   description="Seriallite III Streaming MegaCore Function"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/SerialLite"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="my_compose_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <tag2 key="VALIDATION_CALLBACK" value="my_validation_callback" />
 </component>
 <component
   name="altera_sl3_fanout"
   file="altera_sl3/src/lib/altera_sl3_fanout/altera_sl3_fanout_hw.tcl"
   displayName="SerialLite III Fanout"
   version="25.1"
   description="Altera SL3 Fanout"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SerialLite"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
 </component>
 <component
   name="altera_sl3_phy_adapter"
   file="altera_sl3/src/phy/adapter/altera_sl3_phy_adapter_hw.tcl"
   displayName="SerialLite III Streaming PHY Adapter"
   version="25.1"
   description="SerialLite III Streaming PHY Adapter"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SerialLite"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_sl3_phy_soft"
   file="altera_sl3/src/phy/soft_ip/altera_sl3_phy_soft_hw.tcl"
   displayName="SerialLite III Streaming Phy Soft"
   version="25.1"
   description="SerialLite III Streaming Phy Soft"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SerialLite"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_sl3_phy_top"
   file="altera_sl3/src/phy/top/altera_sl3_phy_top_hw.tcl"
   displayName="Seriallite III Streaming PHY TOP"
   version="25.1"
   description="Sub-Components of Altera Seriallite III Streaming"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SerialLite"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="my_compose_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_sl3_pll_wrapper"
   file="altera_sl3/src/lib/pll_wrapper/altera_sl3_pll_hw.tcl"
   displayName="Seriallite III Streaming PLL Wrapper"
   version="25.1"
   description="Seriallite III Streaming PLL wrapper"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SerialLite"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="my_compose_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_sl3_sink_mac"
   file="altera_sl3/src/sink/altera_sl3_sink_mac_hw.tcl"
   displayName="SerialLite III Streaming Sink MAC"
   version="25.1"
   description="SerialLite III Streaming Sink MAC"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SerialLite"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_sl3_source_mac"
   file="altera_sl3/src/source/altera_sl3_source_mac_hw.tcl"
   displayName="SerialLite III Streaming Source MAC"
   version="25.1"
   description="SerialLite III Streaming Source MAC"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SerialLite"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_sld_agent_endpoint_bridge"
   file="sld/core/endpoint_wrappers/altera_sld_agent_endpoint_bridge_hw.tcl"
   displayName="altera_sld_agent_endpoint_bridge"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_sld_host_endpoint_bridge"
   file="sld/core/endpoint_wrappers/altera_sld_host_endpoint_bridge_hw.tcl"
   displayName="altera_sld_host_endpoint_bridge"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_sld_hub_controller_system"
   file="sld/core/altera_sld_hub_controller_system/altera_sld_hub_controller_system_hw.tcl"
   displayName="SLD Hub Controller System"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="Remote Hardware Debugging over TCP/IP for Altera SoC"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an_693.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1410385117325/mwh1410384469524" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_sld_jtag_hub"
   file="sld/jtag/altera_sld_jtag_hub/altera_sld_jtag_hub_hw.tcl"
   displayName="Altera SLD JTAG Hub"
   version="25.1"
   description="Altera SLD JTAG Hub -- This TCL component will contain the sld_jtag_hub"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="do_elaboration" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="HardCopy II /// APEX20K /// Cyclone V /// MAX9000 /// HardCopy III /// HardCopy IV /// Cyclone 10 LP /// EPC1 /// EPC2 /// eFPGA 28 HPM /// Programmer Dummy Family /// Cyclone IV E /// MAX V /// FLEX6000 /// Arria 10 /// Cyclone III LS /// FLEX10KE /// Soc Series V /// Stratix 10 for Emulator Use /// Arria II GX /// APEX II /// Arria II GZ /// Cyclone II /// FLEX10KB /// FLEX10KA /// Stratix /// MAX7000AE /// Stratix GX /// Cyclone III /// MAX3000A /// ALTERA /// Cyclone IV GX /// Enhanced Configuration Devices /// MAX 10 /// HardCopy Stratix /// MAX II /// Stratix III /// Arria V GZ /// MAX7000S /// Virtual JTAG TAP /// EMBEDDED_PROCESSOR /// ASC devices /// Cyclone /// Stratix II /// Stratix 10 /// FLEX10K /// FLEX8000 /// EXCALIBUR_ARM /// Stratix V /// MAX7000B /// MAX7000A /// ACEX1K /// APEX20KC /// Stratix II GX /// APEX20KE /// Arria GX /// Flash Memory /// Arria V /// None /// Mercury /// Stratix IV" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="altera_sld_jtag_mux"
   file="sld/jtag/altera_sld_jtag_mux/altera_sld_jtag_mux_hw.tcl"
   displayName="altera_sld_jtag_mux"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_sld_splitter"
   file="sld/core/altera_super_splitter/altera_sld_splitter_hw.tcl"
   displayName="Splitter for debug fabric"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_smb"
   file="altera_smb/altera_smb_hw.tcl"
   displayName="Altera Avalon System Management Bus"
   version="25.1"
   description="This component is a two wire serial interface through which various system component devices communicate with each other."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Serial"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_soft_core_jtag_io"
   file="sld/jtag/altera_soft_core_jtag_io/altera_soft_core_jtag_io_hw.tcl"
   displayName="Altera Soft Core JTAG IO"
   version="25.1"
   description="This soft JTAG I/O megafunction, altera_soft_core_jtag_io, provides a standard JTAG interface that controls all JTAG based SLD debug nodes.&lt;br&gt;  Under the hood, it really controls SLD JTAG hub to which SLD debug nodes connect.  Optionally, it provides a signal to select whether SLD JTAG hub is controlled by the JTAG I/O&lt;br&gt;on this megafunction or by the JTAG I/O on the device JTAG hard controller.
A minimal JTAG controller is implemented to allow full operations of tools&lt;br&gt;that communicate to SLD debug nodes connected to SLD JTAG hub.  The IR instructions implemented are BYPASS, IDCODE, USR0, and USR1.&lt;br&gt;All other IR values are mapped to BYPASS.  This JTAG controller returns IDCODE value, 0x020030DD, which is assigned to Altera soft JTAG controller.&lt;br&gt;The tdo output is never tri-stated, which does not conform to the JTAG standard. 
Only one instance of such megafunction is allowed within one project."
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="do_elaboration" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="NATIVE_INTERPRETER" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="HardCopy II /// APEX20K /// Cyclone V /// MAX9000 /// HardCopy III /// HardCopy IV /// Cyclone 10 LP /// EPC1 /// EPC2 /// eFPGA 28 HPM /// Programmer Dummy Family /// Cyclone IV E /// MAX V /// FLEX6000 /// Arria 10 /// Cyclone III LS /// FLEX10KE /// Soc Series V /// Stratix 10 for Emulator Use /// Arria II GX /// APEX II /// Arria II GZ /// Cyclone II /// FLEX10KB /// FLEX10KA /// Stratix /// MAX7000AE /// Stratix GX /// Cyclone III /// MAX3000A /// ALTERA /// Cyclone IV GX /// Enhanced Configuration Devices /// MAX 10 /// HardCopy Stratix /// MAX II /// Stratix III /// Arria V GZ /// MAX7000S /// Virtual JTAG TAP /// EMBEDDED_PROCESSOR /// ASC devices /// Cyclone /// Stratix II /// Stratix 10 /// FLEX10K /// FLEX8000 /// EXCALIBUR_ARM /// Stratix V /// MAX7000B /// MAX7000A /// ACEX1K /// APEX20KC /// Stratix II GX /// APEX20KE /// Arria GX /// Flash Memory /// Arria V /// None /// Mercury /// Stratix IV" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="altera_soft_core_jtag_io Megafunction Online Help"
     type="OTHER"
     url="http://quartushelp.altera.com/14.0/mergedProjects/hdl/mega/mega_file_softcore_jtag_io.htm" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://quartushelp.altera.com/15.1/mergedProjects/hdl/mega/mega_file_softcore_jtag_io.htm" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_soft_lvds"
   file="altera_soft_lvds/altera_soft_lvds_hw.tcl"
   displayName="Soft LVDS IP"
   version="25.1"
   description="Soft LVDS IP using core logic elements."
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/I/O"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="MAX 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sam1394433606063/sam1394433911642" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_stratix10_hps"
   file="altera_hps/s10/altera_hps_stratix_10/altera_hps_stratix_10_hw.tcl"
   displayName="Stratix 10 Hard Processor System"
   version="25.1"
   description="The HPS contains a microprocessor unit (MPU) subsystem with Cuad-core ARM&#194;&#174; Cortex-A56 MPCore processors, flash memory controllers, dedicatedSDRAMcontroller interconnect, on-chip memories, support peripherals, interface peripherals, debug capabilities, and phase-locked loops (PLLs)."
   tags="AUTHORSHIP=Altera Corporation"
   categories="Processors and Peripherals/Hard Processor Systems"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="STRUCTURAL_COMPOSITION_CALLBACK" value="compose_logicalview" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
  <documentUrl
     displayName="HPS User Guide for Stratix 10"
     type="OTHER"
     url="http://www.altera.com/literature/lit-arria-10.jsp" />
 </component>
 <component
   name="altera_stratix10_hps_io"
   file="altera_hps/s10/hps_io/altera_stratix10_hps_io_hw.tcl"
   displayName="altera_stratix10_hps_io"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPRESS_WARNINGS" value="NO_PORTS_AFTER_ELABORATION" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="altera_stratix10_interface_generator"
   file="altera_hps/s10/interface_generator/altera_stratix10_interface_generator_hw.tcl"
   displayName="altera_stratix10_interface_generator"
   version="25.1"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="SUPPRESS_WARNINGS" value="NO_PORTS_AFTER_ELABORATION" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="altera_streaming_sld_hub_controller"
   file="sld/st/altera_streaming_sld_hub_controller/altera_streaming_sld_hub_controller_hw.tcl"
   displayName="SLD Hub Controller"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <documentUrl
     displayName="System Debugging Tools Overview UG"
     type="OTHER"
     url="http://www.altera.com/literature/hb/qts/qts_qii53027.pdf" />
  <documentUrl
     displayName="Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_virtualjtag.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1410385117325/mwh1410384469524" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_streaming_sld_hub_controller_core"
   file="sld/st/altera_streaming_sld_hub_controller/altera_streaming_sld_hub_controller_core_hw.tcl"
   displayName="altera_streaming_sld_hub_controller_core"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_super_splitter"
   file="sld/core/altera_super_splitter/altera_super_splitter_hw.tcl"
   displayName="Splitter for debug fabric"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_sync_reset_shift_register"
   file="merlin/altera_sync_reset_shift_register/altera_sync_reset_shift_register_hw.tcl"
   displayName="altera_sync_reset_shift_register"
   version="25.1"
   description="altera_sync_reset_shift_register"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="altera_sysmgr"
   file="hps/hard_peripheral_logical_view/sysmgr/sysmgr_hw.tcl"
   displayName="Altera System Manager"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="altera_system_max_id"
   file="sld/misc/altera_system_max_id/altera_system_max_id_hw.tcl"
   displayName="altera_system_max_id"
   version="25.1"
   description=""
   tags="AUTHORSHIP= /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_tap_xlate"
   file="sld/trace/monitors/altera_avst_tmon_mlab/altera_tap_xlate_hw.tcl"
   displayName="Avalon ST Tap Translator"
   version="1.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="altera_temp_sense"
   file="altera_temp_sense/altera_temp_sense_hw.tcl"
   displayName="Temperature Sensor IP"
   version="25.1"
   description="The Temperature Sensor megafunction configures the temperature sensing diode (TSD)  block to utilize the temperature measurement feature in the FPGA."
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria V /// Arria V GZ /// Stratix IV /// Stratix V /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/eis1412131558004.html" />
 </component>
 <component
   name="altera_throughput_tap_xlate"
   file="sld/trace/monitors/altera_avst_throughput_monitor/altera_throughput_tap_xlate_hw.tcl"
   displayName="Avalon ST Throughput Tap Translator"
   version="1.0"
   description=""
   tags="AUTHORSHIP= /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
 </component>
 <component
   name="altera_tmon_mlab"
   file="sld/trace/monitors/altera_avst_tmon_mlab/altera_tmon_mlab_hw.tcl"
   displayName="Avalon tmon mlab core"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="NATIVE_INTERPRETER" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="altera_trace"
   file="altera_trace/altera_trace_hw.tcl"
   displayName="HPS External Trace Core IP"
   version="1.0"
   description="This soft IP is used to export the trace interface from HPS out to FPGA IO pin"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="altera_trace_adc_monitor"
   file="sld/trace/monitors/altera_trace_adc_monitor/altera_trace_adc_monitor_hw.tcl"
   displayName="Altera Trace ADC Monitor"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_trace_adc_monitor_core"
   file="sld/trace/monitors/altera_trace_adc_monitor/altera_trace_adc_monitor_core_hw.tcl"
   displayName="Altera Trace ADC Monitor Core"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_trace_adc_monitor_driver"
   file="sld/trace/monitors/altera_trace_adc_monitor/altera_trace_adc_monitor_driver_hw.tcl"
   displayName="altera_trace_adc_monitor_driver"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_trace_adc_monitor_wa"
   file="sld/trace/monitors/altera_trace_adc_monitor/altera_trace_adc_monitor_wa_hw.tcl"
   displayName="Altera Trace ADC Monitor Width Adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_trace_av_st_monitor"
   file="sld/trace/monitors/altera_trace_av_st_example_monitor/altera_trace_av_st_monitor_hw.tcl"
   displayName="avalon streaming monitor"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_trace_av_st_tap"
   file="sld/trace/monitors/altera_trace_av_st_tap/altera_trace_av_st_tap_hw.tcl"
   displayName="avalon streaming to conduit tap"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_trace_av_st_video_pixel_grabber_monitor"
   file="sld/trace/monitors/av_st_video_pixel_grabber/altera_trace_av_st_video_pixel_grabber_monitor_hw.tcl"
   displayName="video pixel sampling monitor"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_trace_capture_controller"
   file="sld/trace/core/altera_trace_capture_controller/altera_trace_capture_controller_hw.tcl"
   displayName="altera_trace_capture_controller"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_trace_channel_mapper"
   file="sld/trace/core/altera_trace_channel_mapper/altera_trace_channel_mapper_hw.tcl"
   displayName="Trace channel mapper"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
 </component>
 <component
   name="altera_trace_controller"
   file="sld/trace/core/altera_trace_controller/altera_trace_controller_hw.tcl"
   displayName="Trace Controller"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_trace_controller_endpoint"
   file="sld/core/endpoint_wrappers/altera_trace_controller_endpoint_hw.tcl"
   displayName="altera_trace_controller_endpoint"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_trace_dummy_monitor"
   file="sld/trace/monitors/altera_trace_dummy_monitor/altera_trace_dummy_monitor_hw.tcl"
   displayName="altera_trace_dummy_monitor"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="altera_trace_fabric"
   file="sld/trace/core/altera_trace_fabric/altera_trace_fabric_hw.tcl"
   displayName="Trace Fabric"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_trace_monitor_endpoint"
   file="sld/core/endpoint_wrappers/altera_trace_monitor_endpoint_hw.tcl"
   displayName="altera_trace_monitor_endpoint"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_trace_monitor_endpoint_bridge"
   file="sld/core/endpoint_wrappers/altera_trace_monitor_endpoint_bridge_hw.tcl"
   displayName="altera_trace_monitor_endpoint_bridge"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_trace_printf_monitor"
   file="sld/trace/monitors/altera_trace_printf_monitor/altera_trace_printf_monitor_hw.tcl"
   displayName="Altera Trace Printf Monitor"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="altera_trace_rom"
   file="sld/trace/core/altera_trace_rom/altera_trace_rom_hw.tcl"
   displayName="Trace ROM"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_trace_stats_gatherer"
   file="sld/trace/monitors/altera_trace_stats_gatherer/altera_trace_stats_gatherer_hw.tcl"
   displayName="Altera Trace Statistics Gatherer"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <component
   name="altera_trace_system"
   file="sld/trace/core/altera_trace_system/altera_trace_system_hw.tcl"
   displayName="Trace System"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411020431690" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505" />
 </component>
 <component
   name="altera_trace_timestamp_monitor"
   file="sld/trace/monitors/altera_trace_ts_module/altera_trace_timestamp_monitor_hw.tcl"
   displayName="Timestamp monitor"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_trace_transacto_lite"
   file="sld/trace/core/altera_trace_transacto_lite/altera_trace_transacto_lite_hw.tcl"
   displayName="transacto_lite"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_trace_trigger_monitor"
   file="sld/trace/monitors/altera_trace_trigger_monitor/altera_trace_trigger_monitor_hw.tcl"
   displayName="Trigger monitor"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_trace_video_monitor"
   file="sld/trace/monitors/altera_trace_video_monitor/altera_trace_video_monitor_hw.tcl"
   displayName="Avalon-ST Video Monitor Core"
   version="25.1"
   description="Monitors an Avalon-ST Video connection to facilitate debug of a video system. Data is captured from the datapath and exposed via one or more Avalon-ST source interfaces"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPOSITION_CALLBACK" value="snoop_composition_callback" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="altera_trace_video_tap_bridge"
   file="sld/trace/monitors/altera_trace_video_tap_bridge/altera_trace_video_tap_bridge_hw.tcl"
   displayName="bridge for av st tap"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance/Trace"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_trace_wrapper"
   file="altera_trace/altera_trace_wrapper_hw.tcl"
   displayName="HPS Trace IP"
   version="25.1"
   description="This soft IP is used to export the trace interface from HPS out to FPGA pin"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Hard Processor Components"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="altera_transacto_fabric"
   file="sld/mm/altera_transacto_fabric/altera_transacto_fabric_hw.tcl"
   displayName="Avalon MM Debug Fabric"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_tristate_conduit_bfm"
   file="sopc_builder_ip/verification/altera_tristate_conduit_bfm/altera_tristate_conduit_bfm_hw.tcl"
   displayName="Tri-State Conduit BFM Intel FPGA IP"
   version="25.1"
   description="Altera Tri-State Conduit BFM"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Avalon Verification Suite"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="PREFERRED_SIMULATION_LANGUAGE" value="none" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1412471932581/nik1412471834211" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_tristate_conduit_bridge"
   file="merlin/altera_tristate_conduit_bridge/altera_tristate_conduit_bridge_hw.tcl"
   displayName="Tri-State Conduit Bridge"
   version="25.1"
   description="Converts between an on-chip encoding of tri-state signals and true bidirectional signals"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset,tristate_conduit"
   categories="Qsys Interconnect/Tri-State Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_avalon_tc.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409959261007" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_tristate_conduit_bridge_translator"
   file="merlin/altera_tristate_conduit_bridge_translator/altera_tristate_conduit_bridge_translator_hw.tcl"
   displayName="Tri-State Conduit Bridge Translator"
   version="25.1"
   description="This component converts false conduit tri-state signals into conduit output signals.  Its primary use is strictly for simulation."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit"
   categories="Tri-State Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409959261007" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_tristate_conduit_pin_sharer"
   file="merlin/altera_tristate_conduit_pin_sharer/altera_tristate_conduit_pin_sharer_hw.tcl"
   displayName="Tri-State Conduit Pin Sharer"
   version="25.1"
   description="Multiplexes between the signals of the connected tri-state controllers"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset,tristate_conduit"
   categories="Tri-State Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_avalon_tc.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409959261007" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_tristate_conduit_pin_sharer_core"
   file="merlin/altera_tristate_conduit_pin_sharer_core/altera_tristate_conduit_pin_sharer_core_hw.tcl"
   displayName="Tri-State Conduit Pin Sharer Core"
   version="25.1"
   description="Multiplexes between the signals of the connected tri-state controllers."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset,tristate_conduit /// INTERNAL_COMPONENT=true"
   categories="Tri-State Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_avalon_tc.pdf" />
 </component>
 <component
   name="altera_tristate_controller_aggregator"
   file="merlin/altera_tristate_controller_aggregator/altera_tristate_controller_aggregator_hw.tcl"
   displayName="Tristate Controller Aggregator"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset,tristate_conduit /// INTERNAL_COMPONENT=true"
   categories="Tristate Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="altera_tristate_controller_translator"
   file="merlin/altera_tristate_controller_translator/altera_tristate_controller_translator_hw.tcl"
   displayName="Tristate Controller Translator"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Tristate Components"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf" />
 </component>
 <component
   name="altera_uflex_ilk"
   file="altera_uflex_interlaken/uflex_ilk_ce_top/altera_uflex_ilk_ce_hw.tcl"
   displayName="Interlaken IP Core (2nd Generation)"
   version="25.1"
   description="Interlaken IP Core (2nd Generation)"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_uflex_ilk_barebone"
   file="altera_uflex_interlaken/uflex_ilk_top/altera_uflex_ilk_hw.tcl"
   displayName="Ultra Flexible Interlaken Core"
   version="25.1"
   description="Altera Ultra Flexible Interlaken Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix V /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="altera_ufm_i2c"
   file="altera_ufm/altera_ufm_i2c/altera_ufm_i2c_hw.tcl"
   displayName="User Flash Memory for I2C Interface Protocol Intel FPGA IP"
   version="25.1"
   description="The Altera User Flash Memory for I2C Interface Protocol megafunction implements the user  non-volatile memory for MAX II/Max V devices using the I2C interface protocol."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="MAX V /// MAX II" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_alt_ufm.pdf" />
 </component>
 <component
   name="altera_ufm_parallel"
   file="altera_ufm/altera_ufm_parallel/altera_ufm_parallel_hw.tcl"
   displayName="User Flash Memory for Parallel Interface Protocol Intel FPGA IP"
   version="25.1"
   description="The Altera User Flash Memory for Parallel Interface Protocol megafunction implements user  non-volatile memory for MAX II/Max V devices using the parallel interface protocol."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="MAX V /// MAX II" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_alt_ufm.pdf" />
 </component>
 <component
   name="altera_ufm_spi"
   file="altera_ufm/altera_ufm_spi/altera_ufm_spi_hw.tcl"
   displayName="User Flash Memory for SPI Interface Protocol Intel FPGA IP"
   version="25.1"
   description="The Altera User Flash Memory for SPI Interface Protocol megafunction implements user  non-volatile memory for MAX II/Max V devices using the SPI interface protocol."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="MAX V /// MAX II" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_alt_ufm.pdf" />
 </component>
 <component
   name="altera_up_altpll"
   file="university_program/clocks/altera_up_altpll/altera_up_altpll_hw.tcl"
   displayName="ALTPLLs for DE-series Board Peripherals"
   version="18.0"
   description="Creates required PLLs for Cyclone III and Cyclone IV DE-series board peripherals"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="University Program/Clock"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <component
   name="altera_up_avalon_accelerometer_spi"
   file="university_program/input_output/altera_up_avalon_accelerometer_spi/altera_up_avalon_accelerometer_spi_hw.tcl"
   displayName="Accelerometer SPI Mode"
   version="18.0"
   description="Accelerometer Controller in SPI Mode for the DE0-Nano Board"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset"
   categories="University Program/Generic IO"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/input_output/altera_up_avalon_accelerometer_spi/doc/Accelerometer_SPI_Mode.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/input_output/altera_up_avalon_accelerometer_spi/doc/Accelerometer_SPI_Mode.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <plugin
   name="altera_up_avalon_accelerometer_spi_driver"
   file="university_program/input_output/altera_up_avalon_accelerometer_spi/altera_up_avalon_accelerometer_spi_sw.tcl"
   displayName="altera_up_avalon_accelerometer_spi_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_accelerometer_spi"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_up_avalon_adc"
   file="university_program/input_output/altera_up_avalon_adc/altera_up_avalon_adc_hw.tcl"
   displayName="ADC Controller for DE-series Boards"
   version="18.0"
   description="ADC Controller for Altera DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="University Program/Generic IO"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/input_output/altera_up_avalon_adc/doc/ADC_Controller.pdf" />
 </component>
 <component
   name="altera_up_avalon_adc_mega"
   file="university_program/input_output/altera_up_avalon_adc/altera_up_avalon_adc_mega_hw.tcl"
   displayName="ADC Controller for DE-series Boards"
   version="18.0"
   description="ADC Controller for Altera DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="University Program/Generic IO"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/input_output/altera_up_avalon_adc/doc/ADC_Controller.pdf" />
 </component>
 <component
   name="altera_up_avalon_audio"
   file="university_program/audio_video/altera_up_avalon_audio/altera_up_avalon_audio_hw.tcl"
   displayName="Audio"
   version="18.0"
   description="Audio Controller for DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,reset"
   categories="University Program/Audio &amp; Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/altera_up_avalon_audio/doc/Audio.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/audio_video/altera_up_avalon_audio/doc/Audio.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_audio_and_video_config"
   file="university_program/audio_video/altera_up_avalon_audio_and_video_config/altera_up_avalon_audio_and_video_config_hw.tcl"
   displayName="Audio and Video Config"
   version="18.0"
   description="I2C bus for audio and video configuration on DE-series boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,conduit,reset"
   categories="University Program/Audio &amp; Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/altera_up_avalon_audio_and_video_config/doc/Audio_and_Video_Config.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file://ip/altera/university_program/audio_video/altera_up_avalon_audio_and_video_config/doc/Audio_and_Video_Config.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_audio_pll"
   file="university_program/clocks/altera_up_avalon_audio_pll/altera_up_avalon_audio_pll_hw.tcl"
   displayName="Audio Clock for DE-series Boards"
   version="18.0"
   description="Creates the required PLL for the audio clock on the DE-series boards"
   tags="AUTHORSHIP=Intel FPGA University Program"
   categories="University Program/Clock"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/clocks/altera_up_avalon_audio_pll/../doc/Altera_UP_Clocks.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file://ip/altera/university_program/clocks/doc/Altera_UP_Clocks.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_character_lcd"
   file="university_program/audio_video/altera_up_avalon_character_lcd/altera_up_avalon_character_lcd_hw.tcl"
   displayName="16x2 Character Display"
   version="18.0"
   description="Character LCD controller for DE2-series boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,conduit,reset"
   categories="University Program/Audio &amp; Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/altera_up_avalon_character_lcd/doc/Character_LCD.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/audio_video/altera_up_avalon_character_lcd/doc/Character_LCD.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_de0_nano_adc"
   file="university_program/input_output/altera_up_avalon_de0_nano_adc/altera_up_avalon_de0_nano_adc_hw.tcl"
   displayName="DE0-Nano ADC Controller"
   version="18.0"
   description="ADC Controller for Altera DE0-Nano Board"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="University Program/Generic IO"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/input_output/altera_up_avalon_de0_nano_adc/doc/DE0-Nano_ADC_Controller.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/input_output/altera_up_avalon_de0_nano_adc/doc/DE0-Nano_ADC_Controller.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_de0_nano_adc_mega"
   file="university_program/input_output/altera_up_avalon_de0_nano_adc/altera_up_avalon_de0_nano_adc_mega_hw.tcl"
   displayName="DE0-Nano ADC Controller"
   version="18.0"
   description="ADC Controller for Altera DE0-Nano Board"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="University Program/Generic IO"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/input_output/altera_up_avalon_de0_nano_adc/doc/DE0-Nano_ADC_Controller.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/input_output/altera_up_avalon_de0_nano_adc/doc/DE0-Nano_ADC_Controller.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_de1_soc_adc"
   file="university_program/input_output/altera_up_avalon_de1_soc_adc/altera_up_avalon_de1_soc_adc_hw.tcl"
   displayName="DE1-SoC ADC Controller"
   version="18.0"
   description="ADC Controller for Altera DE1-SoC Board"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="University Program/Generic IO"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/input_output/altera_up_avalon_de1_soc_adc/doc/DE1-SoC_ADC_Controller.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file://ip/altera/university_program/input_output/altera_up_avalon_de1_soc_adc/doc/DE1-SoC_ADC_Controller.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_de1_soc_adc_mega"
   file="university_program/input_output/altera_up_avalon_de1_soc_adc/altera_up_avalon_de1_soc_adc_mega_hw.tcl"
   displayName="DE1-SoC ADC Controller"
   version="18.0"
   description="ADC Controller for Altera DE1-SoC Board"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="University Program/Generic IO"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/input_output/altera_up_avalon_de1_soc_adc/doc/DE1-SoC_ADC_Controller.pdf" />
 </component>
 <component
   name="altera_up_avalon_irda"
   file="university_program/communication/altera_up_avalon_irda/altera_up_avalon_irda_hw.tcl"
   displayName="IrDA UART"
   version="18.0"
   description="IrDA UART Controller"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,reset"
   categories="University Program/Communications"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/communication/altera_up_avalon_irda/doc/IrDA.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file://ip/altera/university_program/input_output/altera_up_avalon_parallel_port/doc/Parallel_Port.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_parallel_port"
   file="university_program/input_output/altera_up_avalon_parallel_port/altera_up_avalon_parallel_port_hw.tcl"
   displayName="Parallel Port"
   version="18.0"
   description="Parallel Port Interface for Altera DE-Series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,reset"
   categories="University Program/Generic IO"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/input_output/altera_up_avalon_parallel_port/doc/Parallel_Port.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/input_output/altera_up_avalon_ps2/doc/PS2_Controller.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_ps2"
   file="university_program/input_output/altera_up_avalon_ps2/altera_up_avalon_ps2_hw.tcl"
   displayName="PS/2 Controller"
   version="18.0"
   description="PS/2 controller for the DE-Series boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,reset"
   categories="University Program/Generic IO"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/input_output/altera_up_avalon_ps2/doc/PS2_Controller.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/communication/altera_up_avalon_rs232/doc/RS232.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_reset_from_locked_signal"
   file="university_program/clocks/altera_up_avalon_reset_from_locked_signal/altera_up_avalon_reset_from_locked_signal_hw.tcl"
   displayName="Reset from clock locked signal"
   version="18.0"
   description="Creates a reset from the clock locked signal"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=conduit,reset /// INTERNAL_COMPONENT=true"
   categories="University Program/Subcomponents"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
 </component>
 <component
   name="altera_up_avalon_rs232"
   file="university_program/communication/altera_up_avalon_rs232/altera_up_avalon_rs232_hw.tcl"
   displayName="RS232 UART"
   version="17.1"
   description="RS232 UART Controller"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,reset"
   categories="University Program/Communications"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/communication/altera_up_avalon_rs232/doc/RS232.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:////ip/altera/university_program/memory/altera_up_avalon_sram/doc/SRAM_Controller.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_sram"
   file="university_program/memory/altera_up_avalon_sram/altera_up_avalon_sram_hw.tcl"
   displayName="SRAM Controller"
   version="18.0"
   description="SRAM Controller for DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,conduit,reset"
   categories="University Program/Memory"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/memory/altera_up_avalon_sram/doc/SRAM_Controller.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/clocks/doc/Altera_UP_Clocks.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_ssram"
   file="university_program/memory/altera_up_avalon_ssram/altera_up_avalon_ssram_hw.tcl"
   displayName="SSRAM Controller"
   version="18.0"
   description="SSRAM Controller for DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program"
   categories="University Program/Memory"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/memory/altera_up_avalon_ssram/doc/SSRAM_Controller.pdf" />
 </component>
 <component
   name="altera_up_avalon_sys_sdram_pll"
   file="university_program/clocks/altera_up_avalon_sys_sdram_pll/altera_up_avalon_sys_sdram_pll_hw.tcl"
   displayName="System and SDRAM Clocks for DE-series Boards"
   version="18.0"
   description="Creates the required PLL for system and SDRAM clocks on the DE-series boards"
   tags="AUTHORSHIP=Intel FPGA University Program"
   categories="University Program/Clock"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/clocks/altera_up_avalon_sys_sdram_pll/../doc/Altera_UP_Clocks.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/clocks/doc/Altera_UP_Clocks.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_to_external_bus_bridge"
   file="university_program/bridges/altera_up_avalon_to_external_bus_bridge/altera_up_avalon_to_external_bus_bridge_hw.tcl"
   displayName="Avalon to External Bus Bridge"
   version="18.0"
   description="Avalon to External Bus Bridge"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,interrupt,reset"
   categories="University Program/Bridges"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/bridges/altera_up_avalon_to_external_bus_bridge/doc/Avalon_to_External_Bus_Bridge.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/bridges/altera_up_avalon_to_external_bus_bridge/doc/Avalon_to_External_Bus_Bridge.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_usb"
   file="university_program/input_output/altera_up_avalon_usb/altera_up_avalon_usb_hw.tcl"
   displayName="USB Controller"
   version="18.0"
   description="USB controller for the DE-Series boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset"
   categories="University Program/Generic IO"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/input_output/altera_up_avalon_usb/doc/USB.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///acds_releases/acds/15.1/137/linux64/ip/altera/university_program/input_output/altera_up_avalon_usb/doc/USB.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_video_alpha_blender"
   file="university_program/audio_video/video/altera_up_avalon_video_alpha_blender/altera_up_avalon_video_alpha_blender_hw.tcl"
   displayName="Alpha Blender"
   version="18.0"
   description="Alpha Blender (RGBA) for DE-Series boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_alpha_blender/../doc/Video.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411020080713" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505" />
 </component>
 <component
   name="altera_up_avalon_video_ascii_to_image"
   file="university_program/audio_video/video/altera_up_avalon_video_ascii_to_image/altera_up_avalon_video_ascii_to_image_hw.tcl"
   displayName="ASCII to Image Stream"
   version="18.0"
   description="ASCII Characters to Image Stream Converter"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_ascii_to_image/../doc/Video.pdf" />
 </component>
 <component
   name="altera_up_avalon_video_bayer_resampler"
   file="university_program/audio_video/video/altera_up_avalon_video_bayer_resampler/altera_up_avalon_video_bayer_resampler_hw.tcl"
   displayName="Bayer Pattern Resampler"
   version="18.0"
   description="Bayer Pattern Resampler for DE-Series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_bayer_resampler/../doc/Video.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/audio_video/video/doc/Video.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_video_bridge_raw_to_vip_bridge"
   file="university_program/audio_video/video/altera_up_avalon_video_vip_bridges/altera_up_avalon_video_raw_to_vip_bridge_hw.tcl"
   displayName="VIP Bridge: RAW to VIP"
   version="18.0"
   description="VIP Bridge: RAW to VIP"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_vip_bridges/../doc/Video.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/audio_video/video/doc/Video.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_video_bridge_vip_to_raw_bridge"
   file="university_program/audio_video/video/altera_up_avalon_video_vip_bridges/altera_up_avalon_video_vip_to_raw_bridge_hw.tcl"
   displayName="VIP Bridge: VIP to RAW"
   version="18.0"
   description="VIP Bridge: VIP to RAW"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_vip_bridges/../doc/Video.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/audio_video/video/doc/Video.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_video_change_alpha"
   file="university_program/audio_video/video/altera_up_avalon_video_change_alpha/altera_up_avalon_video_change_alpha_hw.tcl"
   displayName="Change Alpha Value"
   version="18.0"
   description="Changes the alpha value for all pixels of a given color"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_change_alpha/../doc/Video.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411020313996" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505" />
 </component>
 <component
   name="altera_up_avalon_video_character_buffer_with_dma"
   file="university_program/audio_video/video/altera_up_avalon_video_character_buffer_with_dma/altera_up_avalon_video_character_buffer_with_dma_hw.tcl"
   displayName="Character Buffer for VGA Display"
   version="18.0"
   description="A buffer for ascii characters to be displayed on a VGA/LCD Screen"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_character_buffer_with_dma/../doc/Video.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file:///ip/altera/university_program/audio_video/video/doc/Video.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <plugin
   name="altera_up_avalon_video_character_buffer_with_dma_driver"
   file="university_program/audio_video/video/altera_up_avalon_video_character_buffer_with_dma/altera_up_avalon_video_character_buffer_with_dma_sw.tcl"
   displayName="altera_up_avalon_video_character_buffer_with_dma_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_video_character_buffer_with_dma"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="altera_up_avalon_video_chroma_resampler"
   file="university_program/audio_video/video/altera_up_avalon_video_chroma_resampler/altera_up_avalon_video_chroma_resampler_hw.tcl"
   displayName="Chroma Resampler"
   version="18.0"
   description="Chroma Resampler for DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_chroma_resampler/../doc/Video.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411020094693" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505" />
 </component>
 <component
   name="altera_up_avalon_video_clipper"
   file="university_program/audio_video/video/altera_up_avalon_video_clipper/altera_up_avalon_video_clipper_hw.tcl"
   displayName="Clipper"
   version="18.0"
   description="Video Clipper for DE-Series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_clipper/../doc/Video.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411020116541" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505" />
 </component>
 <component
   name="altera_up_avalon_video_csc"
   file="university_program/audio_video/video/altera_up_avalon_video_csc/altera_up_avalon_video_csc_hw.tcl"
   displayName="Colour-Space Converter"
   version="18.0"
   description="Colour-Space Converter for DE-Series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_csc/../doc/Video.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411020149781" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505" />
 </component>
 <component
   name="altera_up_avalon_video_decoder"
   file="university_program/audio_video/video/altera_up_avalon_video_decoder/altera_up_avalon_video_decoder_hw.tcl"
   displayName="Video-In Decoder"
   version="18.0"
   description="Video-In Decoder for DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
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     url="${IP_ROOTDIR}/altera/university_program/audio_video/video/altera_up_avalon_video_decoder/../doc/Video.pdf" />
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     type="OTHER"
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altera_up_avalon_video_dma_controller"
   file="university_program/audio_video/video/altera_up_avalon_video_dma_controller/altera_up_avalon_video_dma_controller_hw.tcl"
   displayName="DMA Controller"
   version="18.0"
   description="DMA controller for video processing on DE-Series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
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  <documentUrl
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  <documentUrl
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     type="OTHER"
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 </component>
 <plugin
   name="altera_up_avalon_video_dma_controller_driver"
   file="university_program/audio_video/video/altera_up_avalon_video_dma_controller/altera_up_avalon_video_dma_controller_sw.tcl"
   displayName="altera_up_avalon_video_dma_controller_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_video_dma_controller"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
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   displayName="DMA&apos;s Front and Back Buffer Address Translator"
   version="18.0"
   description="Translates the front and back buffer addresses"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
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  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
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 </component>
 <component
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   file="university_program/audio_video/video/altera_up_avalon_video_dual_clock_buffer/altera_up_avalon_video_dual_clock_buffer_hw.tcl"
   displayName="Dual-Clock FIFO"
   version="18.0"
   description="A Dual-Clock FIFO for DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
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  <documentUrl
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 </component>
 <component
   name="altera_up_avalon_video_edge_detection"
   file="university_program/audio_video/video/altera_up_avalon_video_edge_detection/altera_up_avalon_video_edge_detection_hw.tcl"
   displayName="Edge Detection"
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   description="Video In Edge Detection for DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
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 <component
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   file="university_program/audio_video/video/altera_up_avalon_video_lt24_controller/altera_up_avalon_video_lt24_controller_hw.tcl"
   displayName="LT24 Controller"
   version="18.0"
   description="Controller for the LT24 Screen Peripheral"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset"
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   factory="TclModuleFactory">
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  <documentUrl
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 <component
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   version="18.0"
   description="A DMA Controller for a Pixel Buffer for the DE-series Boards"
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   factory="TclModuleFactory">
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 <component
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   categories="University Program/Clock"
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 </component>
 <component
   name="altera_up_avalon_video_rgb_resampler"
   file="university_program/audio_video/video/altera_up_avalon_video_rgb_resampler/altera_up_avalon_video_rgb_resampler_hw.tcl"
   displayName="RGB Resampler"
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   description="RGB Resampler for DE-series Boards"
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   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
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 <plugin
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   file="university_program/audio_video/video/altera_up_avalon_video_rgb_resampler/altera_up_avalon_video_rgb_resampler_sw.tcl"
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   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_video_rgb_resampler"
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 <component
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   displayName="Scaler"
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   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
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 </component>
 <component
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   file="university_program/audio_video/video/altera_up_avalon_video_stream_router/altera_up_avalon_video_stream_router_hw.tcl"
   displayName="Video-Stream Router"
   version="18.0"
   description="Video-Stream Router for DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
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 </component>
 <component
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   file="university_program/audio_video/video/altera_up_avalon_video_test_pattern/altera_up_avalon_video_test_pattern_hw.tcl"
   displayName="Test-Pattern Generator"
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   factory="TclModuleFactory">
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 <component
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   file="university_program/audio_video/video/altera_up_avalon_video_vga_controller/altera_up_avalon_video_vga_controller_hw.tcl"
   displayName="VGA Controller"
   version="18.0"
   description="VGA controller for DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset"
   categories="University Program/Audio &amp; Video/Video"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_EDITABLE" value="false" />
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 </component>
 <component
   name="altera_up_external_bus_to_avalon_bridge"
   file="university_program/bridges/altera_up_external_bus_to_avalon_bridge/altera_up_external_bus_to_avalon_bridge_hw.tcl"
   displayName="External Bus to Avalon Bridge"
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   description="External Bus to Avalon Bridge"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=avalon,clock,reset"
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   factory="TclModuleFactory">
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     type="OTHER"
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 </component>
 <component
   name="altera_usb_debug_fifos"
   file="sld/usb/altera_usb_debug_fifos/altera_usb_debug_fifos_hw.tcl"
   displayName="USB Debug FIFOs"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Verification/Debug &amp; Performance"
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 </component>
 <component
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   file="sld/usb/altera_usb_debug_link/altera_usb_debug_link_hw.tcl"
   displayName="USB Debug Link"
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   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
   factory="TclModuleFactory">
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     url="http://www.altera.com/literature/hb/qts/qts_qii53028.pdf" />
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 </component>
 <component
   name="altera_usb_debug_link_internal"
   file="sld/usb/altera_usb_debug_link/altera_usb_debug_link_internal_hw.tcl"
   displayName="USB Debug Link (internal module)"
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   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Debug and Performance"
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   file="altera_vectored_interrupt_controller/top/altera_vic_hw.tcl"
   displayName="Vectored Interrupt Controller IP"
   version="25.1"
   description="Vectored Interrupt Controller"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Peripherals"
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   file="altera_vectored_interrupt_controller/csr/altera_vic_csr_hw.tcl"
   displayName="VIC CSR Block IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
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   file="altera_vectored_interrupt_controller/top/altera_vic_sw.tcl"
   displayName="altera_vic_driver"
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   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_vic"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
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   file="altera_vectored_interrupt_controller/priority/altera_vic_priority_hw.tcl"
   displayName="VIC Priority Block IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
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 <component
   name="altera_vic_vector"
   file="altera_vectored_interrupt_controller/vector/altera_vic_vector_hw.tcl"
   displayName="VIC Vector Block IP"
   version="25.1"
   description=""
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   name="altera_vid"
   file="altera_vid/tcl/altera_vid_hw.tcl"
   displayName="SmartVID Controller IP"
   version="25.1"
   description="SmartVID Controller IP"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Low Power"
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The Quartus Prime software or JTAG control host identifies each instance of this megafunction by a unique index. Each megafunction instance
functions in a flow that resembles the JTAG operation of a device. The logic that uses this interface must maintain the continuity of
the JTAG chain on behalf the PLD device when this instance becomes active."
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 <component
   name="altera_viterbi_ii"
   file="dsp/altera_vit_ii/top_hw/altera_viterbi_ii_hw.tcl"
   displayName="Viterbi IP"
   version="25.1"
   description="Altera Viterbi"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
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 <component
   name="altera_voltage_sensor"
   file="altera_voltage_sensor/top/altera_voltage_sensor_hw.tcl"
   displayName="Voltage Sensor IP"
   version="25.1"
   description="Voltage Sensor"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
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 <component
   name="altera_voltage_sensor_control"
   file="altera_voltage_sensor/control/altera_voltage_sensor_control_hw.tcl"
   displayName="Voltage Sensor Control Core IP"
   version="25.1"
   description="Voltage Sensor - Control core"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock,reset /// INTERNAL_COMPONENT=true"
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   file="altera_voltage_sensor/sample_store/altera_voltage_sensor_sample_store_hw.tcl"
   displayName="Voltage Sensor Sample Storage Core IP"
   version="25.1"
   description="Voltage Sensor - Sample Storage core"
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 <component
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   displayName="1G/10GbE and 10GBASE-KR PHY IP"
   version="25.1"
   description="1G/10GE and 10GBASE-KR PHY"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=false"
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 <component
   name="altera_xcvr_10gbaser"
   file="altera_10gbaser_phy/altera_10gbaser_phy/altera_xcvr_10gbaser_hw.tcl"
   displayName="10GBASE-R PHY IP"
   version="25.1"
   description="10GBASE-R PHY IP"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Interface Protocols/Ethernet/10G to 1G Multi-rate Ethernet"
   factory="TclModuleFactory">
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  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
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 <component
   name="altera_xcvr_10gkr_a10"
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   displayName="1G/10GbE and 10GBASE-KR PHY Arria 10 IP"
   version="25.1"
   description="1G/10GE and 10GBASE-KR PHY"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,hssi_serial_clock,reset /// INTERNAL_COMPONENT=false"
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 <component
   name="altera_xcvr_10gkr_s10"
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   displayName="Stratix 10 10GBASE-KR PHY"
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   description="10GBASE-KR PHY"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,hssi_serial_clock,reset /// INTERNAL_COMPONENT=false"
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 <component
   name="altera_xcvr_atx_pll_a10"
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   displayName="Transceiver ATX PLL Arria 10 IP"
   version="25.1"
   description="Arria 10 Transceiver ATX PLL."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,hssi_bonded_clock,hssi_serial_clock,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Transceiver PLL"
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  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
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  <documentUrl
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     type="OTHER"
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 </component>
 <component
   name="altera_xcvr_atx_pll_ip_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER/rtl/pll_atxpll/altera_xcvr_atx_pll_ip_a10.qsys"
   displayName="altera_xcvr_atx_pll_ip_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_xcvr_atx_pll_ip_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER_RegMode/rtl/pll_atxpll/altera_xcvr_atx_pll_ip_a10.qsys"
   displayName="altera_xcvr_atx_pll_ip_a10"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_xcvr_cal_a10"
   file="alt_xcvr/altera_xcvr_cal/altera_xcvr_cal_a10/tcl/altera_xcvr_cal_a10_hw.tcl"
   displayName="Arria10 Transceiver NIOS-Calibration IP"
   version="25.1"
   description="Arria10 Transceiver NIOS Calibration IP"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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     key="ELABORATION_CALLBACK"
     value="::altera_xcvr_cal_a10::module::elaborate" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
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     type="DATASHEET"
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 </component>
 <component
   name="altera_xcvr_cdr_pll_a10"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_cdr_pll_vi/tcl/altera_xcvr_cdr_pll_a10_hw.tcl"
   displayName="Transceiver CMU PLL Arria 10 IP"
   version="25.1"
   description="Arria 10 Transceiver CMU PLL."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,hssi_serial_clock,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Transceiver PLL"
   factory="TclModuleFactory">
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  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_xcvr_cdr_pll_vi::module::elaborate" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
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     type="DATASHEET"
     url="http://www.altera.com/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf" />
  <documentUrl
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     type="OTHER"
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  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697765829" />
 </component>
 <component
   name="altera_xcvr_custom_phy"
   file="altera_xcvr_8g_custom/xcvr_generic/altera_xcvr_custom_phy_hw.tcl"
   displayName="Custom PHY Intel FPGA IP"
   version="19.1"
   description="Standard Transceiver PCS Custom PHY IP"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
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  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="validate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
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 </component>
 <component
   name="altera_xcvr_det_latency"
   file="altera_xcvr_det_latency/xcvr_generic/altera_xcvr_det_latency_hw.tcl"
   displayName="Deterministic Latency PHY Intel FPGA IP"
   version="19.1"
   description="Deterministic Latency PHY IP"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
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  <tag2 key="ANALYZE_HDL" value="false" />
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  <documentUrl
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     type="DATASHEET"
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 </component>
 <component
   name="altera_xcvr_dl_soft_pcs"
   file="altera_xcvr_det_latency/soft_pcs/altera_xcvr_dl_soft_pcs_hw.tcl"
   displayName="Deterministic Latency Soft PCS PHY"
   version="25.1"
   description="Deterministic Latency PHY IP with soft PCS"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
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  <documentUrl
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     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
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 <component
   name="altera_xcvr_fpll_a10"
   file="alt_xcvr/altera_xcvr_pll/altera_xcvr_fpll_vi/tcl/altera_xcvr_fpll_a10_hw.tcl"
   displayName="fPLL Arria 10 IP"
   version="25.1"
   description="Arria 10 FPLL."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,hssi_bonded_clock,hssi_serial_clock,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Transceiver PLL"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
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     value="::altera_xcvr_fpll_vi::module::elaborate" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_xcvr_fpll_vi::module::upgrade" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
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     type="DATASHEET"
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  <documentUrl
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     type="OTHER"
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697750806" />
 </component>
 <component
   name="altera_xcvr_interlaken"
   file="alt_interlaken/alt_interlaken_pcs/altera_xcvr_interlaken_hw.tcl"
   displayName="Interlaken PHY"
   version="25.1"
   description="A multiple-lane Interlaken PCS component with integrated PMA and management layers"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_low_latency_phy"
   file="alt_pma/source/altera_xcvr_low_latency_phy/altera_xcvr_low_latency_phy_hw.tcl"
   displayName="Low Latency PHY Intel FPGA IP"
   version="25.1"
   description="Standard Transceiver PCS Low Latency PHY IP"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
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  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_native_a10"
   file="alt_xcvr/altera_xcvr_native_phy/altera_xcvr_native_vi/tcl/altera_xcvr_native_a10_hw.tcl"
   displayName="Transceiver Native PHY Arria 10 IP"
   version="25.1"
   description="Arria 10 Transceiver Native PHY."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_xcvr_native_vi::module::elaborate" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_xcvr_native_vi::parameters::upgrade" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
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     type="DATASHEET"
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1398707230472/nik1398706811600" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697772894" />
 </component>
 <component
   name="altera_xcvr_native_av"
   file="alt_xcvr/altera_xcvr_native_phy/av/tcl/altera_xcvr_native_av_hw.tcl"
   displayName="Arria V Transceiver Native PHY Intel FPGA IP"
   version="19.1"
   description="Arria V Transceiver Native PHY."
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_xcvr_native_av::module::elaborate" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_xcvr_native_av::parameters::upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_native_avgz"
   file="alt_xcvr/altera_xcvr_native_phy/avgz/tcl/altera_xcvr_native_avgz_hw.tcl"
   displayName="Arria V GZ Transceiver Native PHY Intel FPGA IP"
   version="19.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_xcvr_native_avgz::module::elaborate" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_xcvr_native_sv::parameters::upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_native_cv"
   file="alt_xcvr/altera_xcvr_native_phy/cv/tcl/altera_xcvr_native_cv_hw.tcl"
   displayName="Transceiver Native PHY Intel Cyclone V FPGA IP"
   version="19.1"
   description="Cyclone V Transceiver Native PHY."
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_xcvr_native_cv::module::elaborate" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_xcvr_native_cv::parameters::upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_native_sv"
   file="alt_xcvr/altera_xcvr_native_phy/sv/tcl/altera_xcvr_native_sv_hw.tcl"
   displayName="Transceiver Native PHY Intel Stratix V FPGA IP"
   version="19.1"
   description="Stratix V Transceiver Native PHY."
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_xcvr_native_sv::module::elaborate" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_xcvr_native_sv::parameters::upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_pcie_hip_native_s10"
   file="alt_xcvr/altera_xcvr_pcie_hip_native/altera_xcvr_pcie_hip_native_s10/altera_xcvr_pcie_hip_native_s10_hw.tcl"
   displayName="Altera Transciever PCIe HIP Native"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_xcvr_pcie_hip_native_s10::altera_xcvr_pcie_hip_native_s10_elab_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2
     key="VALIDATION_CALLBACK"
     value="::altera_xcvr_pcie_hip_native_s10::altera_xcvr_pcie_hip_native_s10_val_callback" />
 </component>
 <component
   name="altera_xcvr_pipe"
   file="altera_pcie_pipe/xcvr_generic/altera_xcvr_pipe_hw.tcl"
   displayName="PHY for PCI Express (PIPE) Intel FPGA IP"
   version="25.1"
   description="Implements the PCS and PMA modules as defined by the Intel PHY Interface for PCI Express (PIPE) Architecture specification."
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_pll_av"
   file="alt_xcvr/altera_xcvr_pll/av/tcl/altera_xcvr_pll_av_hw.tcl"
   displayName="Arria V Transceiver PLL Intel FPGA IP"
   version="19.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ELABORATION_CALLBACK"
     value="::altera_xcvr_pll_av::module::elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_pll_avgz"
   file="alt_xcvr/altera_xcvr_pll/avgz/tcl/altera_xcvr_pll_avgz_hw.tcl"
   displayName="Arria V GZ Transceiver PLL Intel FPGA IP"
   version="19.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
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  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <documentUrl
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     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_pll_cv"
   file="alt_xcvr/altera_xcvr_pll/cv/tcl/altera_xcvr_pll_cv_hw.tcl"
   displayName="Cyclone V Transceiver PLL Intel FPGA IP"
   version="19.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
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  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_pll_sv"
   file="alt_xcvr/altera_xcvr_pll/sv/tcl/altera_xcvr_pll_sv_hw.tcl"
   displayName="Stratix V Transceiver PLL Intel FPGA IP"
   version="19.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
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  <documentUrl
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     type="DATASHEET"
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 </component>
 <component
   name="altera_xcvr_reset_control"
   file="alt_xcvr/altera_xcvr_reset_control/tcl/altera_xcvr_reset_control_hw.tcl"
   displayName="Transceiver PHY Reset Controller IP"
   version="20.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
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  <tag2
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  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
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     type="OTHER"
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  <documentUrl
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  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/nik1398707230472/nik1398706951368" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300" />
 </component>
 <component
   name="altera_xcvr_reset_control_s10"
   file="alt_xcvr/altera_xcvr_reset_control_s10/tcl/altera_xcvr_reset_control_s10_hw.tcl"
   displayName="Transceiver PHY Reset Controller Stratix 10 IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
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  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
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     type="OTHER"
     url="http://www.altera.com/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf" />
  <documentUrl
     displayName="Documentation (Stratix V/Cyclone V/Arria V/Arria V GZ)"
     type="OTHER"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="altera_xcvr_reset_controller_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE/rtl/xcvr_reset_controller/altera_xcvr_reset_controller_a10.qsys"
   displayName="altera_xcvr_reset_controller_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_xcvr_reset_controller_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/xcvr_reset_controller/altera_xcvr_reset_controller_a10.qsys"
   displayName="altera_xcvr_reset_controller_a10"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
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 </component>
 <component
   name="altera_xcvr_reset_controller_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE/rtl/xcvr_reset_controller/altera_xcvr_reset_controller_a10.qsys"
   displayName="altera_xcvr_reset_controller_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_xcvr_reset_controller_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/xcvr_reset_controller/altera_xcvr_reset_controller_a10.qsys"
   displayName="altera_xcvr_reset_controller_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="altera_xcvr_reset_sequencer_s10"
   file="sld/si_fixes/alt_xcvr/altera_xcvr_reset_sequencer/altera_xcvr_reset_sequencer_s10/altera_xcvr_reset_sequencer_s10_hw.tcl"
   displayName="Altera Stratix 10 Transceiver Reset Sequencer"
   version="25.1"
   description="Altera Stratix 10 Transceiver Reset Sequencer"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="do_elaboration" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="HardCopy II /// APEX20K /// Cyclone V /// MAX9000 /// HardCopy III /// HardCopy IV /// Cyclone 10 LP /// EPC1 /// EPC2 /// eFPGA 28 HPM /// Programmer Dummy Family /// Cyclone IV E /// MAX V /// FLEX6000 /// Arria 10 /// Cyclone III LS /// FLEX10KE /// Soc Series V /// Stratix 10 for Emulator Use /// Arria II GX /// APEX II /// Arria II GZ /// Cyclone II /// FLEX10KB /// FLEX10KA /// Stratix /// MAX7000AE /// Stratix GX /// Cyclone III /// MAX3000A /// ALTERA /// Cyclone IV GX /// Enhanced Configuration Devices /// MAX 10 /// HardCopy Stratix /// MAX II /// Stratix III /// Arria V GZ /// MAX7000S /// Virtual JTAG TAP /// EMBEDDED_PROCESSOR /// ASC devices /// Cyclone /// Stratix II /// Stratix 10 /// FLEX10K /// FLEX8000 /// EXCALIBUR_ARM /// Stratix V /// MAX7000B /// MAX7000A /// ACEX1K /// APEX20KC /// Stratix II GX /// APEX20KE /// Arria GX /// Flash Memory /// Arria V /// None /// Mercury /// Stratix IV" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="altera_xcvr_xaui"
   file="alt_xaui/lib/altera_xcvr_xaui_hw.tcl"
   displayName="XAUI PHY IP"
   version="25.1"
   description="XGMII to XAUI transceiver"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Ethernet/10G to 1G Multi-rate Ethernet"
   factory="TclModuleFactory">
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  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix IV /// Stratix V /// Cyclone IV GX /// Arria V /// Cyclone V /// Arria II GX /// Arria II GZ /// Arria V GZ /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
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     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/nik1398707230472.html#mta1400546865132" />
  <documentUrl
     displayName="User Guide (other families)"
     type="OTHER"
     url="https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/hco1421698012332.html" />
 </component>
 <component
   name="altmemmult"
   file="megafunctions/altmemmult/altmemmult_hw.tcl"
   displayName="ALTMEMMULT Intel FPGA IP"
   version="25.1"
   description="altmemmult"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sam1395331197196/sam1395329539091" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altmult_complex"
   file="megafunctions/altmult_complex/altmult_complex_hw.tcl"
   displayName="ALTMULT_COMPLEX Intel FPGA IP"
   version="25.1"
   description="The ALTERA_MULT_COMPLEX megafunction allows you to implement a multiplier-complex"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
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  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="parameter_upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sam1395331401937/sam1395329571445" />
  <documentUrl
     displayName="User Guide For Stratix 10"
     type="OTHER"
     url="https://documentation.altera.com/#/link/kly1436148709581/kly1439175970736" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/ktw1517822281214.html" />
 </component>
 <component
   name="altpcie_devkit"
   file="altera_pcie/altera_pcie_a10_ed/devkit/altpcie_devkit_hw.tcl"
   displayName="Development Kit : Pinout drivers Intel FPGA IP"
   version="25.1"
   description="Interface Protocols/PCI Express/QSYS Example Designs"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express/QSYS Example Designs"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2
     key="ICON_PATH"
     value="${IP_ROOTDIR}/altera/altera_pcie/altera_pcie_a10_ed/devkit/A10Devkit.jpg" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.1" />
 </component>
 <component
   name="altpcied_sriov_mbox_hw"
   file="altera_pcie/altera_pcie_sriov_dma_avmm/altpcied_sriov_mbox/altpcied_sriov_mbox_hw.tcl"
   displayName="Example : PCIe SR-IOV Mailbox"
   version="25.1"
   description="Example : PCIe SR-IOV Mailbox for interrupt and LMI"
   tags="AUTHORSHIP=PCIe IPD /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express/Example Design Components"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V GZ /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-01161-1.0.pdf" />
 </component>
 <component
   name="altpll"
   file="sopc_builder_ip/altera_avalon_altpll/altera_avalon_altpll_hw.tcl"
   displayName="ALTPLL Intel FPGA IP"
   version="25.1"
   description="Avalon-compatible Intel PLL module. For Stratix V and newer families, use Intel FPGA PLL IP"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon,clock,conduit"
   categories="Basic Functions/Clocks; PLLs and Resets/PLL"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="EDITOR_CALLBACK" value="do_edit" />
  <tag2 key="ELABORATION_CALLBACK" value="do_elaboration" />
  <tag2 key="GENERATION_CALLBACK" value="do_generation" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Arria II GX /// Arria II GZ /// Stratix IV /// Cyclone IV E /// Cyclone IV GX /// MAX 10 /// Cyclone 10 LP" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.0" />
  <tag2 key="VALIDATION_CALLBACK" value="do_validation" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sam1412657969844/sam1412657677094" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altpll_reconfig"
   file="sopc_builder_ip/altera_avalon_altpll_reconfig/altera_avalon_altpll_reconfig_hw.tcl"
   displayName="ALTPLL RECONFIG Intel FPGA IP"
   version="25.1"
   description="Avalon-compatible PLL RECONFIG Intel FPGA IP. For Stratix V and newer families, use PLL RECONFIG Intel FPGA IP"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/Clocks; PLLs and Resets/PLL"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="EDITOR_CALLBACK" value="do_edit" />
  <tag2 key="ELABORATION_CALLBACK" value="do_elaboration" />
  <tag2 key="GENERATION_CALLBACK" value="do_generation" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="MAX 10" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.0" />
  <tag2 key="VALIDATION_CALLBACK" value="do_validation" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/en_US/pdfs/literature/hb/max-10/ug_m10_clkpll.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altshift_taps"
   file="megafunctions/altshift_taps/altshift_taps_hw.tcl"
   displayName="Shift Register (RAM-based) Intel FPGA IP"
   version="25.1"
   description="altshift_taps"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_shift_register_ram_based.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/en_US/pdfs/literature/ug/ug_shift_register_ram_based.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="altsqrt"
   file="megafunctions/altsqrt/altsqrt_hw.tcl"
   displayName="ALTSQRT"
   version="25.1"
   description="altsqrt"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link//sam1395329597887/sam1395331471570" />
  <documentUrl
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 </component>
 <plugin
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   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="apb"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="apb_master"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="APB Master"
   version="25.1"
   description="APB master interfaces are used to issue read and write commands to slave interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
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 <plugin
   name="apb_slave"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="APB Slave"
   version="25.1"
   description="APB slave interfaces are used to accept and respond to read and write commands issued by master interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
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 <component
   name="arm_a9"
   file="hps/hard_peripheral_logical_view/arm_a9/arm_a9_hw.tcl"
   displayName="ARM A9"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
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 </component>
 <component
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   file="hps/hard_peripheral_logical_view/arm_gic/arm_gic_hw.tcl"
   displayName="ARM GIC"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
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 <component
   name="arm_internal_timer"
   file="hps/hard_peripheral_logical_view/timer/timer_hw.tcl"
   displayName="ARM internal timer"
   version="25.1"
   description=""
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   categories=""
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   file="hps/hard_peripheral_logical_view/l2/l2_hw.tcl"
   displayName="ARM pl310 cache"
   version="25.1"
   description=""
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 <component
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   file="hps/hard_peripheral_logical_view/dma/dma_hw.tcl"
   displayName="ARM pl330 dma"
   version="25.1"
   description=""
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   categories=""
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  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
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   file="altera_hps/altera_hps_arria_10/gic/arm_gic_hw.tcl"
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   description=""
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  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <plugin
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   file="alt_xcvr/altera_xcvr_reset_control/tcl/arria10_default.qprs"
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   description=""
   tags=""
   categories=""
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 </plugin>
 <component
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   file="altera_hps/altera_hps_arria_10/hps_bridge_avalon/hps_bridge_avalon_hw.tcl"
   displayName="HPS Bridge Avalon"
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   categories=""
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  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
 </component>
 <plugin
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   file="alt_xcvr/altera_xcvr_reset_control/tcl/arria10_no_sequencing.qprs"
   displayName="arria10_no_sequencing.qprs"
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   description=""
   tags=""
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 </plugin>
 <component
   name="asimov_clkmgr"
   file="hps/hard_peripheral_logical_view/clkmgr/clkmgr_hw.tcl"
   displayName="Altera Clock Manager"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
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  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="ast2avmm_bridge_256"
   file="altera_pcie/altera_pcie_a10_ed/ast2avmm_bridge_256/ast2avmm_bridge_256_hw.tcl"
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   description="256 Bits AST to AVMM Bridge with Burst RX Master, TX Slave and CRA Interfaces"
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   categories="Interface Protocols/PCI Express/QSYS Example Designs"
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  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="15.1" />
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 <component
   name="atx_pll_e50g"
   file="ethernet/alt_e2550/example_project/common/atx_pll_e50g.qsys"
   displayName="atx_pll_e50g"
   version="1.0"
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   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
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 <component
   name="audio_embed"
   file="audio_ip/audio_embed/audio_embed_hw.tcl"
   displayName="Audio Embed Intel FPGA IP"
   version="25.1"
   description="Audio Embed"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Audio &amp; Video"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697950421" />
 </component>
 <component
   name="audio_extract"
   file="audio_ip/audio_extract/audio_extract_hw.tcl"
   displayName="Audio Extract Intel FPGA IP"
   version="25.1"
   description="Audio Extract"
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   categories="Interface Protocols/Audio &amp; Video"
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 <plugin
   name="avalon"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="avalon"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="avalon"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Avalon Memory Mapped Connection"
   version="25.1"
   description="An Avalon Memory Mapped connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
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 <plugin
   name="avalon_adc_driver"
   file="university_program/input_output/altera_up_avalon_adc/altera_up_avalon_adc_sw.tcl"
   displayName="avalon_adc_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_adc"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="avalon_character_lcd_driver"
   file="university_program/audio_video/altera_up_avalon_character_lcd/altera_up_avalon_character_lcd_sw.tcl"
   displayName="avalon_character_lcd_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_character_lcd"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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 <plugin
   name="avalon_de0_nano_adc_driver"
   file="university_program/input_output/altera_up_avalon_de0_nano_adc/altera_up_avalon_de0_nano_adc_sw.tcl"
   displayName="avalon_de0_nano_adc_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_de0_nano_adc"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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 <plugin
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   file="university_program/input_output/altera_up_avalon_de1_soc_adc/altera_up_avalon_de1_soc_adc_sw.tcl"
   displayName="avalon_de1_soc_adc_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_de1_soc_adc"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="avalon_master"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Avalon Memory Mapped Master"
   version="25.1"
   description="Memory Mapped master interfaces are used to issue read and write commands to slave interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
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 <plugin
   name="avalon_parallel_port_driver"
   file="university_program/input_output/altera_up_avalon_parallel_port/altera_up_avalon_parallel_port_sw.tcl"
   displayName="avalon_parallel_port_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_parallel_port"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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 <plugin
   name="avalon_slave"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Avalon Memory Mapped Slave"
   version="25.1"
   description="Memory Mapped slave interfaces are used to accept and respond to read and write commands issued by master interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="avalon_streaming"
   file="dsp/lib/helpers/com.altera.sopcmodel.atlantic.jar"
   displayName="avalon_streaming"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="avalon_streaming"
   file="dsp/lib/helpers/com.altera.sopcmodel.atlantic.jar"
   displayName="Avalon Streaming Connection"
   version="25.1"
   description="An Avalon Streaming Connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="avalon_streaming_sink"
   file="dsp/lib/helpers/com.altera.sopcmodel.atlantic.jar"
   displayName="Avalon Streaming Sink"
   version="25.1"
   description="Avalon Streaming Sink Interfaces are used to accept streaming data."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
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 <plugin
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   file="dsp/lib/helpers/com.altera.sopcmodel.atlantic.jar"
   displayName="Avalon Streaming Source"
   version="25.1"
   description="Avalon Streaming Source Interfaces are used to provide streaming data. "
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
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   file="dsp/lib/helpers/com.altera.sopcmodel.atlantic.jar"
   displayName="avalon_streaming_video"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
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   file="dsp/lib/helpers/com.altera.sopcmodel.atlantic.jar"
   displayName="Avalon Streaming Video Sink"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
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 <plugin
   name="avalon_streaming_video_source"
   file="dsp/lib/helpers/com.altera.sopcmodel.atlantic.jar"
   displayName="Avalon Streaming Video Source"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
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 <plugin
   name="avalon_video_pixel_buffer_dma_driver"
   file="university_program/audio_video/video/altera_up_avalon_video_pixel_buffer_dma/altera_up_avalon_video_pixel_buffer_dma_sw.tcl"
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   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_video_pixel_buffer_dma"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
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 <component
   name="avl_mem_addr_adaption"
   file="pgm/altera_asmi_parallel2_top/avl_mem_addr_adaption_hw.tcl"
   displayName="ASMI2 addr adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
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  <tag2 key="VALIDATION_CALLBACK" value="validate" />
 </component>
 <plugin
   name="axi"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="axi"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="axi4"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="axi4"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="axi4lite"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="axi4lite"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="axi4stream"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="axi4stream"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="axi4stream"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="AXI4 Stream Connection"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="axi4stream_master"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="AXI 4 Stream Master"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <component
   name="axi_ocram"
   file="hps/hard_peripheral_logical_view/axi_ocram/axi_ocram_hw.tcl"
   displayName="HPS On Chip RAM"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="axi_sdram"
   file="hps/hard_peripheral_logical_view/axi_sdram/axi_sdram_hw.tcl"
   displayName="SDRAM connected to HPS"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="baum_clkmgr"
   file="altera_hps/altera_hps_arria_10/clkmgr/clkmgr_hw.tcl"
   displayName="Altera Clock Manager"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
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  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="bitec_hdmi_rx"
   file="altera_hdmi/src/rx/bitec_hdmi_rx_hw.tcl"
   displayName="Altera HDMI RX Protocol"
   version="25.1"
   description="Altera HDMI RX Protocol"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/HDMI/Altera HDMI RX Protocol"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
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  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="bitec_hdmi_tx"
   file="altera_hdmi/src/tx/bitec_hdmi_tx_hw.tcl"
   displayName="Altera HDMI TX Protocol"
   version="25.1"
   description="Altera HDMI TX Protocol"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/HDMI/Altera HDMI TX Protocol"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
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 </component>
 <component
   name="bosch_dcan"
   file="hps/hard_peripheral_logical_view/dcan/dcan_hw.tcl"
   displayName="Bosch DCAN"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
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  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="byte_order"
   file="alt_xcvr/alt_xcvr_ip_lib/alt_xcvr_byte_order/byte_order_hw.tcl"
   displayName="Design Example Byte Order"
   version="14.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="byte_order_elab_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <tag2 key="VALIDATION_CALLBACK" value="byte_order_val_callback" />
 </component>
 <component
   name="cadence_qspi"
   file="hps/hard_peripheral_logical_view/qspi/qspi_hw.tcl"
   displayName="Cadence QSPI"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
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  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="cfbp_g1x8_ast64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/cfbp_g1x8_ast64.qsys"
   displayName="cfbp_g1x8_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="cfbp_g2x8_ast128"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/cfbp_g2x8_ast128.qsys"
   displayName="cfbp_g2x8_ast128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="cfbp_g3x8_ast256"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/cfbp_g3x8_ast256.qsys"
   displayName="cfbp_g3x8_ast256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="channel_adapter"
   file="avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl"
   displayName="Avalon-ST Channel Adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
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     type="OTHER"
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  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="clark_clkmgr"
   file="altera_hps/s10/clkmgr/clkmgr_hw.tcl"
   displayName="Altera Clock Manager"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="clkrec_pll135_a10"
   file="altera_dp/de_gen/arria_10/rtl/clkrec/clkrec_pll135_a10.qsys"
   displayName="clkrec_pll135_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="clkrec_pll_a10"
   file="altera_dp/de_gen/arria_10/rtl/clkrec/clkrec_pll_a10.qsys"
   displayName="clkrec_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="clkrec_pll_a10"
   file="altera_dp/hw_demo/common/clkrec/clkrec_pll_a10.qsys"
   displayName="clkrec_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="clkrec_reset_a10"
   file="altera_dp/de_gen/arria_10/rtl/clkrec/clkrec_reset_a10.qsys"
   displayName="clkrec_reset_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="clkrec_reset_a10"
   file="altera_dp/hw_demo/common/clkrec/clkrec_reset_a10.qsys"
   displayName="clkrec_reset_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="clock"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="clock"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="clock"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Clock Connection"
   version="25.1"
   description="A clock connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="clock"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Clock"
   version="25.1"
   description="A clock connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <component
   name="clock_source"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Clock Source"
   version="25.1"
   description="A clock output interface drives a clock signal out of a component. Clock output interfaces cannot have reset signals."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   factory="BeanElementFactory" />
 <component
   name="clocked_audio_input"
   file="audio_ip/clocked_audio_input/clocked_audio_input_hw.tcl"
   displayName="Clocked Audio Input Intel FPGA IP"
   version="25.1"
   description="Clocked Audio Input"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Audio &amp; Video"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix /// Stratix GX /// Stratix II /// Stratix II GX /// Stratix III /// Stratix IV /// Stratix V /// Arria GX /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// HardCopy IV /// Cyclone /// Cyclone II /// Cyclone III /// Cyclone III LS /// Cyclone IV E /// Cyclone IV GX /// Cyclone V" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/sam1425277356256/sam1425277101341" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697950421" />
 </component>
 <component
   name="clocked_audio_output"
   file="audio_ip/clocked_audio_output/clocked_audio_output_hw.tcl"
   displayName="Clocked Audio Output Intel FPGA IP"
   version="25.1"
   description="Clocked Audio Output"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon_streaming,clock,conduit /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Audio &amp; Video"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2
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  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/sam1425277356256/sam1425277101341" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697950421" />
 </component>
 <plugin
   name="conduit"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="conduit"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="conduit"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Conduit Connection"
   version="25.1"
   description="A conduit connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="conduit"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Conduit Endpoint"
   version="7.1"
   description="A conduit connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <component
   name="conduit_splitter"
   file="gx_debug/conduit_splitter/conduit_splitter_hw.tcl"
   displayName="Conduit splitter"
   version="25.1"
   description="A conduit signal splitter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Peripherals/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_embedded_ip.pdf" />
 </component>
 <component
   name="configure_reconfig"
   file="ethernet/altera_eth_10g_design_example/design_example_components/base_kr/configure_reconfig_hw.tcl"
   displayName="configure_reconfig"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Ethernet/Reference Designs/Reference Design Components"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="control"
   file="altera_dp/hw_demo/av_sk_4k/control.qsys"
   displayName="control"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="control"
   file="altera_dp/hw_demo/cv/control.qsys"
   displayName="control"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=false"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="control"
   file="altera_dp/hw_demo/mst_av_sk_4k/control.qsys"
   displayName="control"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="control"
   file="altera_dp/hw_demo/mst_sv/control.qsys"
   displayName="control"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="control"
   file="altera_dp/hw_demo/sv/control.qsys"
   displayName="control"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="core_pll"
   file="altera_jesd204/ed/ed_sim/scripts/core_pll.qsys"
   displayName="core_pll"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="core_pll_reconfig"
   file="altera_jesd204/ed/ed_sim/scripts/core_pll_reconfig.qsys"
   displayName="core_pll_reconfig"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="data_format_adapter"
   file="avalon_st/altera_avalon_st_data_format_adapter/avalon-st_data_format_adapter_hw.tcl"
   displayName="Avalon-ST Data Format Adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <plugin
   name="data_sink"
   file="sopc_builder_ip/altera_avalon_data_sink/data_sink_sw.tcl"
   displayName="data_sink"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=data_sink"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="data_source"
   file="sopc_builder_ip/altera_avalon_data_source/data_source_sw.tcl"
   displayName="data_source"
   version="25.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=data_source"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="dc_fifo_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER/rtl/fifo_dcfifo/dc_fifo_a10.qsys"
   displayName="dc_fifo_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="dc_fifo_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER_RegMode/rtl/fifo_dcfifo/dc_fifo_a10.qsys"
   displayName="dc_fifo_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="ddr3.qprs"
   file="emif/hwtcl/altera_emif/ddr3.qprs"
   displayName="ddr3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif" />
 </plugin>
 <plugin
   name="ddr3.qprs"
   file="emif/hwtcl/altera_emif_a10_hps/ddr3.qprs"
   displayName="ddr3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif_a10_hps" />
 </plugin>
 <plugin
   name="ddr3.qprs"
   file="emif/hwtcl/altera_emif_s10/ddr3.qprs"
   displayName="ddr3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif_s10" />
 </plugin>
 <plugin
   name="ddr3.qprs"
   file="emif/hwtcl/altera_emif_s10_hps/ddr3.qprs"
   displayName="ddr3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif_s10_hps" />
 </plugin>
 <plugin
   name="ddr3.qprs"
   file="emif/ip_top/presets/ddr3.qprs"
   displayName="ddr3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="ip_top" />
 </plugin>
 <plugin
   name="ddr3_devkit.qprs"
   file="emif/hwtcl/altera_emif/ddr3_devkit.qprs"
   displayName="ddr3_devkit.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif" />
 </plugin>
 <plugin
   name="ddr3_devkit.qprs"
   file="emif/ip_top/presets/ddr3_devkit.qprs"
   displayName="ddr3_devkit.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="ip_top" />
 </plugin>
 <plugin
   name="ddr4.qprs"
   file="emif/hwtcl/altera_emif/ddr4.qprs"
   displayName="ddr4.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif" />
 </plugin>
 <plugin
   name="ddr4.qprs"
   file="emif/hwtcl/altera_emif_a10_hps/ddr4.qprs"
   displayName="ddr4.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif_a10_hps" />
 </plugin>
 <plugin
   name="ddr4.qprs"
   file="emif/hwtcl/altera_emif_s10/ddr4.qprs"
   displayName="ddr4.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif_s10" />
 </plugin>
 <plugin
   name="ddr4.qprs"
   file="emif/hwtcl/altera_emif_s10_hps/ddr4.qprs"
   displayName="ddr4.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif_s10_hps" />
 </plugin>
 <plugin
   name="ddr4.qprs"
   file="emif/ip_top/presets/ddr4.qprs"
   displayName="ddr4.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="ip_top" />
 </plugin>
 <plugin
   name="ddr4_devkit.qprs"
   file="emif/hwtcl/altera_emif/ddr4_devkit.qprs"
   displayName="ddr4_devkit.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif" />
 </plugin>
 <plugin
   name="ddr4_devkit.qprs"
   file="emif/ip_top/presets/ddr4_devkit.qprs"
   displayName="ddr4_devkit.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="ip_top" />
 </plugin>
 <plugin
   name="default.qprs"
   file="alt_xcvr/altera_xcvr_reset_control/tcl/default.qprs"
   displayName="default.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_reset_control" />
 </plugin>
 <plugin
   name="default.qprs"
   file="alt_xcvr/altera_xcvr_reset_control_s10/tcl/default.qprs"
   displayName="default.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_reset_control_s10" />
 </plugin>
 <component
   name="demo_control_a10_duplex"
   file="seriallite_iii/example/example_design/demo_control/demo_control_a10_duplex.qsys"
   displayName="demo_control_a10_duplex"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="demo_control_a10_simplex"
   file="seriallite_iii/example/example_design/demo_control/demo_control_a10_simplex.qsys"
   displayName="demo_control_a10_simplex"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="demo_control_sv_duplex"
   file="seriallite_iii/example/example_design/demo_control/demo_control_sv_duplex.qsys"
   displayName="demo_control_sv_duplex"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="demo_control_sv_simplex"
   file="seriallite_iii/example/example_design/demo_control/demo_control_sv_simplex.qsys"
   displayName="demo_control_sv_simplex"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="demultiplexer"
   file="avalon_st/altera_avalon_st_demultiplexer/avalon-st_demultiplexer_hw.tcl"
   displayName="Avalon-ST Demultiplexer"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401396936060" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="denali_nand"
   file="hps/hard_peripheral_logical_view/denali_nand/denali_nand_hw.tcl"
   displayName="Denali NAND"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="designware_i2c"
   file="hps/hard_peripheral_logical_view/designware_i2c/designware_i2c_hw.tcl"
   displayName="Synopsys I2C"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="dma_control"
   file="altera_pcie/altera_pcie_hip_256_avmm/dynamic_controller/dma_control_hw.tcl"
   displayName="Example : DMA Descriptor Controller for PCI Express"
   version="25.1"
   description="Descriptor Control module manages Read and Write DMA operations. Host software programs this component."
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI Express/Example Design Components"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V /// Cyclone V /// Arria V GZ /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
  <documentUrl
     displayName="Arria 10 AVMM DMA Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_a10_pcie_avmm_dma.pdf" />
  <documentUrl
     displayName="Arria V GZ AVMM DMA Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_a5gz_pcie_avmm_dma.pdf" />
  <documentUrl
     displayName="Stratix V AVMM DMA Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_s5_pcie_avmm_dma.pdf" />
  <documentUrl
     displayName="Arria V Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_a5_pcie.pdf" />
  <documentUrl
     displayName="Cyclone V Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_c5_pcie.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="dma_read_master"
   file="altera_msgdma/read_master/read_master_hw.tcl"
   displayName="Read Master IP"
   version="25.1"
   description="A module responsible for streaming data from memory"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/DMA/mSGDMA Sub-core"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate_me" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_me" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/dmi1420813268955/dmi1421419198649" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="dma_write_master"
   file="altera_msgdma/write_master/write_master_hw.tcl"
   displayName="Write Master IP"
   version="25.1"
   description="A module responsible for writing streaming data to memory"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock /// INTERNAL_COMPONENT=false"
   categories="Basic Functions/DMA/mSGDMA Sub-core"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate_me" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_me" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/dmi1420813268955/dmi1421419198649" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="dut"
   file="vip/verification/dut/dut.qsys"
   displayName="dut"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="dw_apb_timer_osc"
   file="hps/hard_peripheral_logical_view/dw_apb_timer_osc/dw_apb_timer_osc_hw.tcl"
   displayName="Synopsys OCS Timer"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="dw_apb_timer_sp"
   file="hps/hard_peripheral_logical_view/dw_apb_timer_sp/dw_apb_timer_sp_hw.tcl"
   displayName="Synopsys SP Timer"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="dw_gpio"
   file="hps/hard_peripheral_logical_view/dw_gpio/dw_gpio_hw.tcl"
   displayName="Synopsys GPIO"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="dw_wd_timer"
   file="hps/hard_peripheral_logical_view/wd_timer/wd_timer_hw.tcl"
   displayName="Synopsys WatchDog Timer"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="dx_altera_xcvr_native_a10"
   file="alt_xcvr/altera_xcvr_native_phy/dx_altera_xcvr_native_a10/dx_altera_xcvr_native_a10_hw.tcl"
   displayName="Arria 10 Design Example: Transceiver Native PHY"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elab_callback" />
  <tag2
     key="PARAMETER_UPGRADE_CALLBACK"
     value="::altera_xcvr_native_vi::parameters::upgrade" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Arria 10" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="ep_g1x1"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g1x1.qsys"
   displayName="ep_g1x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x1"
   file="altera_pcie/altera_pcie_avgz_hip_avmm/example_designs/ep_g1x1.qsys"
   displayName="ep_g1x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x1"
   file="altera_pcie/altera_pcie_av_hip_avmm/example_designs/ep_g1x1.qsys"
   displayName="ep_g1x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x1"
   file="altera_pcie/altera_pcie_cv_hip_avmm/example_designs/ep_g1x1.qsys"
   displayName="ep_g1x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x1"
   file="altera_pcie/altera_pcie_sv_hip_avmm/example_designs/ep_g1x1.qsys"
   displayName="ep_g1x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x1_625MHz"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g1x1_625MHz.qsys"
   displayName="ep_g1x1_625MHz"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x1_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g1x1_avmm64.qsys"
   displayName="ep_g1x1_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x1avmm_cvp"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g1x1avmm_cvp.qsys"
   displayName="ep_g1x1avmm_cvp"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x2"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g1x2.qsys"
   displayName="ep_g1x2"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x4"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g1x4.qsys"
   displayName="ep_g1x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x4"
   file="altera_pcie/altera_pcie_avgz_hip_avmm/example_designs/ep_g1x4.qsys"
   displayName="ep_g1x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x4"
   file="altera_pcie/altera_pcie_av_hip_avmm/example_designs/ep_g1x4.qsys"
   displayName="ep_g1x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x4"
   file="altera_pcie/altera_pcie_cv_hip_avmm/example_designs/ep_g1x4.qsys"
   displayName="ep_g1x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x4"
   file="altera_pcie/altera_pcie_sv_hip_avmm/example_designs/ep_g1x4.qsys"
   displayName="ep_g1x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x4_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g1x4_avmm64.qsys"
   displayName="ep_g1x4_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x8"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g1x8.qsys"
   displayName="ep_g1x8"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x8"
   file="altera_pcie/altera_pcie_avgz_hip_avmm/example_designs/ep_g1x8.qsys"
   displayName="ep_g1x8"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x8"
   file="altera_pcie/altera_pcie_av_hip_avmm/example_designs/ep_g1x8.qsys"
   displayName="ep_g1x8"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x8"
   file="altera_pcie/altera_pcie_sv_hip_avmm/example_designs/ep_g1x8.qsys"
   displayName="ep_g1x8"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g1x8_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g1x8_avmm64.qsys"
   displayName="ep_g1x8_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x1"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g2x1.qsys"
   displayName="ep_g2x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x1"
   file="altera_pcie/altera_pcie_avgz_hip_avmm/example_designs/ep_g2x1.qsys"
   displayName="ep_g2x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x1"
   file="altera_pcie/altera_pcie_av_hip_avmm/example_designs/ep_g2x1.qsys"
   displayName="ep_g2x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x1"
   file="altera_pcie/altera_pcie_cv_hip_avmm/example_designs/ep_g2x1.qsys"
   displayName="ep_g2x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x1"
   file="altera_pcie/altera_pcie_sv_hip_avmm/example_designs/ep_g2x1.qsys"
   displayName="ep_g2x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x1_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g2x1_avmm64.qsys"
   displayName="ep_g2x1_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x1_cvp"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g2x1_cvp.qsys"
   displayName="ep_g2x1_cvp"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x2"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g2x2.qsys"
   displayName="ep_g2x2"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x4"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g2x4.qsys"
   displayName="ep_g2x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x4"
   file="altera_pcie/altera_pcie_avgz_hip_avmm/example_designs/ep_g2x4.qsys"
   displayName="ep_g2x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x4"
   file="altera_pcie/altera_pcie_av_hip_avmm/example_designs/ep_g2x4.qsys"
   displayName="ep_g2x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x4"
   file="altera_pcie/altera_pcie_cv_hip_avmm/example_designs/ep_g2x4.qsys"
   displayName="ep_g2x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x4"
   file="altera_pcie/altera_pcie_sv_hip_avmm/example_designs/ep_g2x4.qsys"
   displayName="ep_g2x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x4_avmm128"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g2x4_avmm128.qsys"
   displayName="ep_g2x4_avmm128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x4_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g2x4_avmm64.qsys"
   displayName="ep_g2x4_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x8"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g2x8.qsys"
   displayName="ep_g2x8"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x8"
   file="altera_pcie/altera_pcie_avgz_hip_avmm/example_designs/ep_g2x8.qsys"
   displayName="ep_g2x8"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x8"
   file="altera_pcie/altera_pcie_sv_hip_avmm/example_designs/ep_g2x8.qsys"
   displayName="ep_g2x8"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g2x8_avmm128"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g2x8_avmm128.qsys"
   displayName="ep_g2x8_avmm128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g3x1"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g3x1.qsys"
   displayName="ep_g3x1"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g3x2"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g3x2.qsys"
   displayName="ep_g3x2"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g3x4"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g3x4.qsys"
   displayName="ep_g3x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g3x4_avmm128_integrated"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g3x4_avmm128_integrated.qsys"
   displayName="ep_g3x4_avmm128_integrated"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g3x8"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g3x8.qsys"
   displayName="ep_g3x8"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g3x8_ast_pio"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g3x8_ast_pio.qsys"
   displayName="ep_g3x8_ast_pio"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g3x8_avmm256"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g3x8_avmm256.qsys"
   displayName="ep_g3x8_avmm256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ep_g3x8_avmm256_integrated"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/ep_g3x8_avmm256_integrated.qsys"
   displayName="ep_g3x8_avmm256_integrated"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="error_adapter"
   file="avalon_st/altera_avalon_st_error_adapter/avalon-st_error_adapter_hw.tcl"
   displayName="Avalon-ST Error Adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="fifo"
   file="megafunctions/fifo/fifo_hw.tcl"
   displayName="FIFO"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_fifo.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_fifo.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <plugin
   name="fpoint2_driver"
   file="altera_nios_custom_instr_floating_point_2/altera_nios_custom_instr_floating_point_2/fpoint2_qsys_sw.tcl"
   displayName="fpoint2_driver"
   version="13.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal,ucosii /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_nios_custom_instr_floating_point_2"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="freertos"
   file="soft_processor/aws_freertos/freertos_hal2_sw.tcl"
   displayName="FreeRTOS"
   version="25.1"
   description=""
   tags=""
   categories="os_software_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="frequency_counter"
   file="gx_debug/frequency_counter/frequency_counter_hw.tcl"
   displayName="Frequency Counter"
   version="25.1"
   description="Frequency Counter"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock /// INTERNAL_COMPONENT=true"
   categories="Peripherals/Debug and Performance"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="9.1" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/ug_embedded_ip.pdf" />
 </component>
 <plugin
   name="hal2"
   file="soft_processor/altera_hal2/altera_hal_sw.tcl"
   displayName="Altera HAL"
   version="25.1"
   description=""
   tags=""
   categories="os_software_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="hcx_rom_bridge"
   file="alt_mem_if/altera_mem_if_qseq/hcx_rom_bridge/rom_bridge_hw.tcl"
   displayName="hcx_rom_bridge"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="hdmi_rx"
   file="altera_hdmi/hw_demo/av_sk/hdmi_rx/hdmi_rx.qsys"
   displayName="hdmi_rx"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="hdmi_rx"
   file="altera_hdmi/hw_demo/av_sk_hdmi2/hdmi_rx/hdmi_rx.qsys"
   displayName="hdmi_rx"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="hdmi_rx"
   file="altera_hdmi/hw_demo/sv_hdmi2/hdmi_rx/hdmi_rx.qsys"
   displayName="hdmi_rx"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="hdmi_rx_4sym"
   file="altera_hdmi/sim_example/hdmi_rx_4sym.qsys"
   displayName="hdmi_rx_4sym"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="hdmi_tx"
   file="altera_hdmi/hw_demo/av_sk/hdmi_tx/hdmi_tx.qsys"
   displayName="hdmi_tx"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="hdmi_tx"
   file="altera_hdmi/hw_demo/av_sk_hdmi2/hdmi_tx/hdmi_tx.qsys"
   displayName="hdmi_tx"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="hdmi_tx"
   file="altera_hdmi/hw_demo/sv_hdmi2/hdmi_tx/hdmi_tx.qsys"
   displayName="hdmi_tx"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="hdmi_tx_4sym"
   file="altera_hdmi/sim_example/hdmi_tx_4sym.qsys"
   displayName="hdmi_tx_4sym"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="hip_c4gx_gen1x4_qsys"
   file="altera_pcie/altera_pcie_avmm/example_designs/c4gx_gen1x4/hip_c4gx_gen1x4_qsys.qsys"
   displayName="hip_c4gx_gen1x4_qsys"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="hip_s4gx_gen1x8_qsys"
   file="altera_pcie/altera_pcie_avmm/example_designs/s4gx_gen1x8/hip_s4gx_gen1x8_qsys.qsys"
   displayName="hip_s4gx_gen1x8_qsys"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="hps_bridge_avalon"
   file="hps/hard_peripheral_logical_view/hps_bridge_avalon/hps_bridge_avalon_hw.tcl"
   displayName="HPS Bridge Avalon"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="hps_clk_src"
   file="hps/hard_peripheral_logical_view/hps_clk_src/hps_clk_src_hw.tcl"
   displayName="HPS clk src"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <component
   name="hps_virt_clk"
   file="hps/hard_peripheral_logical_view/hps_virt_clk/hps_virt_clk_hw.tcl"
   displayName="HPS Virtual Clock"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.1" />
 </component>
 <plugin
   name="hssi_bonded_clock"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="hssi_bonded_clock"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="hssi_bonded_clock"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="HSSI Bonded Clock Connection"
   version="25.1"
   description="A HSSI Bonded Clock connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="hssi_bonded_clock_sink"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="HSSI Bonded Clock Input"
   version="25.1"
   description="A high speed bonded clock input "
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="hssi_bonded_clock_source"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="HSSI Bonded Clock Output"
   version="25.1"
   description="A high speed bonded clock output "
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="hssi_serial_clock"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="hssi_serial_clock"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="hssi_serial_clock"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="HSSI Serial Clock Connection"
   version="25.1"
   description="A HSSI Serial Clock connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="hssi_serial_clock_sink"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="HSSI Serial Clock Input"
   version="25.1"
   description="A high speed serial clock input "
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="hssi_serial_clock_source"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="HSSI Serial Clock Output"
   version="25.1"
   description="A high speed serial clock output "
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <component
   name="i2c_gpio_buf"
   file="altera_dp/de_gen/arria_10/rtl/i2c_gpio_buf.qsys"
   displayName="i2c_gpio_buf"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="ilk_core"
   file="alt_interlaken_hp/ilk_top/ilk_core_hw.tcl"
   displayName="100G Interlaken IP"
   version="25.1"
   description="100G Interlaken IP"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade_proc" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V GZ /// Arria 10" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_proc" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/nik1411008397235.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/hco1421697730308.html" />
  <documentUrl
     displayName="Example Design - User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/dsu1459187112348.html" />
 </component>
 <component
   name="ilk_core_50g"
   file="alt_interlaken_hp/ilk_50g_top/ilk_core_50g_hw.tcl"
   displayName="50G Interlaken IP"
   version="25.1"
   description="50G Interlaken IP"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Interlaken"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade_proc" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V GZ /// Arria 10" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_proc" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/nik1411004570087.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/hco1421697721554.html" />
  <documentUrl
     displayName="Example Design - User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/dsu1459187448902.html" />
 </component>
 <component
   name="intel_espi_slave"
   file="espi_slave/espi_slave_hw.tcl"
   displayName="eSPI slave IP"
   version="25.1"
   description="This IP is used to communicate between Platform Controller Hub (PCH) ESPI master and peripherals"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Serial"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="intel_espi_to_lpc_bridge"
   file="espi_to_lpc_bridge/espi_to_lpc_bridge_hw.tcl"
   displayName="eSPI to LPC bridge IP"
   version="25.1"
   description="This IP is used to communicate between Platform Controller Hub (PCH) ESPI master and peripherals"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Serial"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
 </component>
 <component
   name="intel_generic_serial_flash_interface_addr"
   file="pgm/intel_generic_serial_flash_interface/intel_generic_serial_flash_interface_addr/intel_generic_serial_flash_interface_addr_hw.tcl"
   displayName="Generic QSPI Addr Adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,reset /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
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   description=""
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon_streaming,clock,conduit,reset /// INTERNAL_COMPONENT=true"
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   description=""
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   description=""
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   tags="SW_DRIVER_OS_TYPE=hal,ucosii,freertos /// SW_DRIVER_ASSOCIATED_HW_MODULE=intel_lw_uart"
   categories="driver_element"
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   categories="Processors and Peripherals/Embedded Processors"
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   tags="SW_DRIVER_OS_TYPE=hal2 /// SW_DRIVER_ASSOCIATED_HW_MODULE=intel_niosv_g"
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 <plugin
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   tags="SW_DRIVER_OS_TYPE=freertos /// SW_DRIVER_ASSOCIATED_HW_MODULE=intel_niosv_m"
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   type="com.altera.entityinterfaces.IElementClass"
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   description=""
   tags="SW_DRIVER_OS_TYPE=hal2 /// SW_DRIVER_ASSOCIATED_HW_MODULE=intel_niosv_m"
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   type="com.altera.entityinterfaces.IElementClass"
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   tags="SW_DRIVER_OS_TYPE=ucosii_hal2 /// SW_DRIVER_ASSOCIATED_HW_MODULE=intel_niosv_m"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
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   displayName="Nios V/m Processor IP"
   version="26.0.0"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Processors and Peripherals/Embedded Processors"
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 <component
   name="intel_niosv_timer_msip"
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   displayName="Nios V Timer and Software Interrupt IP"
   version="1.2.0"
   description="This module houses timer and software interrupt generators for the Nios V Processor."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=avalon,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Processors and Peripherals/Embedded Processors"
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  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
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   displayName="Audio LR Clock for DE-series Boards"
   version="18.0"
   description="Audio LR Clock for DE-series Boards"
   tags="AUTHORSHIP=Intel FPGA University Program /// CONNECTION_TYPES=clock,reset"
   categories="University Program/Clock"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="GENERATION_CALLBACK" value="generate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="${IP_ROOTDIR}/altera/university_program/clocks/intel_up_avalon_audio_clks/../doc/Altera_UP_Clocks.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="file://ip/altera/university_program/clocks/doc/Altera_UP_Clocks.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco142169801340" />
 </component>
 <plugin
   name="interrupt"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="interrupt"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="interrupt"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Interrupt Connection"
   version="25.1"
   description="An interrupt connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="interrupt"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Interrupt"
   version="25.1"
   description="An interrupt connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <component
   name="interrupt_latency_counter"
   file="altera_interrupt_latency_calculator/interrupt_latency_counter_hw.tcl"
   displayName="Interrupt Latency Counter IP"
   version="25.1"
   description="This component measures the time taken from the moment an IRQ signal is fired till the Interrupt Service Routine begins in clock cycle"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Processors and Peripherals/Inter-Process Communication"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/lro1402071729562" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="io_pll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/pll_mpll/io_pll_a10.qsys"
   displayName="io_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="io_pll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/pll_mpll/io_pll_a10.qsys"
   displayName="io_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
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   file="alt_interlaken_hp/testbench/example_design_50g_a10_board_level/jtag_master.qsys"
   displayName="jtag_master"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="kr_cpu_s10"
   file="alt_xcvr/altera_xcvr_10gbase_kr/stratix10/cpu/kr_cpu_s10_hw.tcl"
   displayName="kr_cpu_s10"
   version="1.0"
   description="default description"
   tags="AUTHORSHIP=author /// INTERNAL_COMPONENT=true"
   categories="default group"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="kr_dbg_cpu_s10"
   file="alt_xcvr/altera_xcvr_10gbase_kr/stratix10/cpu/kr_dbg_cpu_s10_hw.tcl"
   displayName="kr_dbg_cpu_s10"
   version="1.0"
   description="default description"
   tags="AUTHORSHIP=author /// INTERNAL_COMPONENT=true"
   categories="default group"
   factory="TclModuleFactory">
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  <tag2 key="COMPOSITION_CALLBACK" value="compose" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
 </component>
 <component
   name="low_latency_baser_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER_RegMode/rtl/phy/low_latency_baser_a10.qsys"
   displayName="low_latency_baser_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="lpddr3.qprs"
   file="emif/hwtcl/altera_emif/lpddr3.qprs"
   displayName="lpddr3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif" />
 </plugin>
 <plugin
   name="lpddr3.qprs"
   file="emif/hwtcl/altera_emif_s10/lpddr3.qprs"
   displayName="lpddr3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif_s10" />
 </plugin>
 <plugin
   name="lpddr3.qprs"
   file="emif/ip_top/presets/lpddr3.qprs"
   displayName="lpddr3.qprs"
   version="0.0"
   description=""
   tags=""
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   type="com.altera.sopcmodel.util.IElementPresetList"
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="ip_top" />
 </plugin>
 <component
   name="lpm_clshift"
   file="megafunctions/lpm_clshift/lpm_clshift_hw.tcl"
   displayName="LPM_CLSHIFT"
   version="25.1"
   description="lpm_clshift"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Miscellaneous"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/catalogs/lpm.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://quartushelp.altera.com/14.1/master.htm#mergedProjects/hdl/mega/mega_file_lpm_clshift.htm" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="lpm_counter"
   file="megafunctions/lpm_counter/lpm_counter_hw.tcl"
   displayName="LPM_COUNTER"
   version="25.1"
   description="Binary counter that creates up counters, down counters and up or down counters with outputs of up to 256 bits width."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="lpm_decode"
   file="megafunctions/lpm_decode/lpm_decode_hw.tcl"
   displayName="LPM_DECODE"
   version="25.1"
   description="lpm_decode"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Miscellaneous"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/catalogs/lpm.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="http://quartushelp.altera.com/14.1/master.htm#mergedProjects/hdl/mega/mega_file_lpm_decode.htm" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="lpm_divide"
   file="megafunctions/lpm_divide/lpm_divide_hw.tcl"
   displayName="LPM_DIVIDE"
   version="25.1"
   description="lpm_divide"
   tags="AUTHORSHIP=Altera    Corporation"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="lpm_mult"
   file="megafunctions/lpm_mult/lpm_mult_hw.tcl"
   displayName="LPM_MULT FPGA IP"
   version="25.1"
   description="Multiplier for two input data values and produces a product as an output."
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=conduit"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="parameter_upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="User Guide For Stratix 10"
     type="OTHER"
     url="https://documentation.altera.com/#/link/kly1436148709581/kly1439175970736" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/ktw1517822281214.html" />
 </component>
 <component
   name="lpm_shiftreg"
   file="megafunctions/lpm_shiftreg/lpm_shiftreg_hw.tcl"
   displayName="LPM_SHIFTREG"
   version="25.1"
   description="lpm_shiftreg"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Miscellaneous"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/catalogs/lpm.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link//mwh1411016588444" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="ltpi"
   file="ltpi/tcl/ltpi_hw.tcl"
   displayName="LVDS Tunneling Protocol and Interface IP"
   version="25.1"
   description="LTPI is a protocol and interface designed for tunneling various low-speed signals between the HPM and SCM"
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon,clock,conduit,reset /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/LTPI"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="::ltpi::module::elaborate" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="MAX 10" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,SIM_VERILOG,EXAMPLE_DESIGN,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/844310.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/docs/programmable/844195.html" />
 </component>
 <plugin
   name="lvds_presets.qprs"
   file="altera_lvds/top/presets/lvds_presets.qprs"
   displayName="lvds_presets.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
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   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="top" />
 </plugin>
 <component
   name="m10_trk_mgr"
   file="alt_mem_if/altera_mem_if_qseq/m10_trk_mgr/sequencer_trk_mgr_m10_hw.tcl"
   displayName="Max10 Tracking Manager"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
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  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="master_export"
   file="altera_sl3/ed/ed_synth/src/demo_control/master_export_hw.tcl"
   displayName="Master Export Pass-Through Component"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="master_export"
   file="seriallite_iii/example/example_design/demo_control/master_export_hw.tcl"
   displayName="Master Export Pass-Through Component"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="mc_top_g3x8_4ch"
   file="altera_pcie/altera_pcie_hip_256_avmm/channelizer/example_design/mc_top_g3x8_4ch.qsys"
   displayName="mc_top_g3x8_4ch"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="merlin_avalon_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="Avalon-MM Merlin Transform"
   version="25.1"
   description="Constructs Merlin interconnects by running a list of appropriate transforms"
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
   factory="BeanElementFactory" />
 <plugin
   name="merlin_domain_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="Merlin Domain Transform"
   version="25.1"
   description="Inserts network interface and network modules "
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
   factory="BeanElementFactory" />
 <plugin
   name="merlin_interrupt_mapper_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="Interrupt Mapper Transform"
   version="25.1"
   description="Inserts interrupt mappers for interrupt receivers with fan-in"
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
   factory="BeanElementFactory" />
 <plugin
   name="merlin_interrupt_sync_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="Interrupt Clock Crosser Transform"
   version="25.1"
   description="Inserts interrupt synchronizers on clock domain crossings"
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
   factory="BeanElementFactory" />
 <plugin
   name="merlin_network_to_switch_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="Packet Switch Transform"
   version="25.1"
   description="Replaces network modules with packet switches "
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
   factory="BeanElementFactory" />
 <plugin
   name="merlin_pipeline_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="com.altera.sopcmodel.transforms.avalon.PipelineTransform"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
   factory="BeanElementFactory" />
 <plugin
   name="merlin_router_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="Merlin Router Transform"
   version="25.1"
   description="Inserts routers"
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
   factory="BeanElementFactory" />
 <plugin
   name="merlin_traffic_limiter_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="Merlin Traffic Limiter Transform"
   version="25.1"
   description="Inserts traffic limiters "
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
   factory="BeanElementFactory" />
 <plugin
   name="merlin_width_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="Merlin Width Transform"
   version="25.1"
   description="Inserts width adapters"
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
   factory="BeanElementFactory" />
 <component
   name="mgc_axi4_inline_monitor"
   file="mentor_vip_ae/axi4/bfm/mgc_axi4_inline_monitor_hw.tcl"
   displayName="Mentor Graphics AXI4 Inline Monitor BFM (Intel FPGA Edition)"
   version="2020.1.0.1"
   description="Mentor Graphics AXI4 Inline Monitor BFM (Intel FPGA Edition)"
   tags="AUTHORSHIP=Mentor Graphics Corporation /// CONNECTION_TYPES=axi4,clock,reset"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaborate" />
  <tag2
     key="ICON_PATH"
     value="${IP_ROOTDIR}/altera/mentor_vip_ae/common/Mentor_VIP_AE_icon.png" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="AXI4 Inline Monitor BFM Reference Guide"
     type="OTHER"
     url="http://www.altera.com/literature/ug/mentor_vip_axi34_ae_usr.pdf" />
 </component>
 <component
   name="mgc_axi4_master"
   file="mentor_vip_ae/axi4/bfm/mgc_axi4_master_hw.tcl"
   displayName="Mentor Graphics AXI4 Master BFM (Intel FPGA Edition)"
   version="2020.1.0.1"
   description="Mentor Graphics AXI4 Master BFM (Intel FPGA Edition)"
   tags="AUTHORSHIP=Mentor Graphics Corporation /// CONNECTION_TYPES=axi4,clock,reset"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaborate" />
  <tag2
     key="ICON_PATH"
     value="${IP_ROOTDIR}/altera/mentor_vip_ae/common/Mentor_VIP_AE_icon.png" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="AXI4 Master BFM Reference Guide"
     type="OTHER"
     url="https://www.altera.com/literature/ug/mentor_vip_ae_usr.pdf" />
 </component>
 <component
   name="mgc_axi4_slave"
   file="mentor_vip_ae/axi4/bfm/mgc_axi4_slave_hw.tcl"
   displayName="Mentor Graphics AXI4 Slave BFM (Intel FPGA Edition)"
   version="2020.1.0.1"
   description="Mentor Graphics AXI4 Slave BFM (Intel FPGA Edition)"
   tags="AUTHORSHIP=Mentor Graphics Corporation /// CONNECTION_TYPES=axi4,clock,reset"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaborate" />
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     value="${IP_ROOTDIR}/altera/mentor_vip_ae/common/Mentor_VIP_AE_icon.png" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="AXI4 Slave BFM Reference Guide"
     type="OTHER"
     url="https://www.altera.com/literature/ug/mentor_vip_ae_usr.pdf" />
 </component>
 <component
   name="mgc_axi4lite_inline_monitor"
   file="mentor_vip_ae/axi4lite/bfm/mgc_axi4lite_inline_monitor_hw.tcl"
   displayName="Mentor Graphics AXI4-Lite Inline Monitor BFM (Intel FPGA Edition)"
   version="2020.1.0.1"
   description="Mentor Graphics AXI4-Lite Inline Monitor BFM (Intel FPGA Edition)"
   tags="AUTHORSHIP=Mentor Graphics Corporation /// CONNECTION_TYPES=axi4lite,clock,reset"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaborate" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
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     type="OTHER"
     url="http://www.altera.com/literature/ug/mentor_vip_axi4lite_ae_usr.pdf" />
 </component>
 <component
   name="mgc_axi4lite_master"
   file="mentor_vip_ae/axi4lite/bfm/mgc_axi4lite_master_hw.tcl"
   displayName="Mentor Graphics AXI4-Lite Master BFM (Intel FPGA Edition)"
   version="2020.1.0.1"
   description="Mentor Graphics AXI4-Lite Master BFM (Intel FPGA Edition)"
   tags="AUTHORSHIP=Mentor Graphics Corporation /// CONNECTION_TYPES=axi4lite,clock,reset"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
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  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
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     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/mentor_vip_axi4lite_ae_usr.pdf" />
 </component>
 <component
   name="mgc_axi4lite_slave"
   file="mentor_vip_ae/axi4lite/bfm/mgc_axi4lite_slave_hw.tcl"
   displayName="Mentor Graphics AXI4-Lite Slave BFM (Intel FPGA Edition)"
   version="2020.1.0.1"
   description="Mentor Graphics AXI4-Lite Slave BFM (Intel FPGA Edition)"
   tags="AUTHORSHIP=Mentor Graphics Corporation /// CONNECTION_TYPES=axi4lite,clock,reset"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaborate" />
  <tag2
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     value="${IP_ROOTDIR}/altera/mentor_vip_ae/common/Mentor_VIP_AE_icon.png" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="AXI4-Lite Slave BFM Reference Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/mentor_vip_axi4lite_ae_usr.pdf" />
 </component>
 <component
   name="mgc_axi4stream_inline_monitor"
   file="mentor_vip_ae/axi4stream/bfm/mgc_axi4stream_inline_monitor_hw.tcl"
   displayName="Siemens AXI4STREAM Inline Monitor BFM (Intel FPGA Edition)"
   version="2020.1.0.1"
   description="Siemens AXI4STREAM Inline Monitor BFM (Intel FPGA Edition)"
   tags="AUTHORSHIP=Siemens /// CONNECTION_TYPES=axi4stream,clock,reset"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaborate" />
  <tag2
     key="ICON_PATH"
     value="${IP_ROOTDIR}/altera/mentor_vip_ae/common/Mentor_VIP_AE_icon.png" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="AXI4STREAM Inline Monitor BFM Reference Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/mentor_vip_axi4_stream_ae_usr.pdf" />
 </component>
 <component
   name="mgc_axi4stream_master"
   file="mentor_vip_ae/axi4stream/bfm/mgc_axi4stream_master_hw.tcl"
   displayName="Siemens AXI4STREAM Master BFM (Intel FPGA Edition)"
   version="2020.1.0.1"
   description="Siemens AXI4STREAM Master BFM (Intel FPGA Edition)"
   tags="AUTHORSHIP=Siemens /// CONNECTION_TYPES=axi4stream,clock,reset"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaborate" />
  <tag2
     key="ICON_PATH"
     value="${IP_ROOTDIR}/altera/mentor_vip_ae/common/Mentor_VIP_AE_icon.png" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="AXI4STREAM Master BFM Reference Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/mentor_vip_axi4_stream_ae_usr.pdf" />
 </component>
 <component
   name="mgc_axi4stream_slave"
   file="mentor_vip_ae/axi4stream/bfm/mgc_axi4stream_slave_hw.tcl"
   displayName="Siemens AXI4STREAM Slave BFM (Intel FPGA Edition)"
   version="2020.1.0.1"
   description="Siemens AXI4STREAM Slave BFM (Intel FPGA Edition)"
   tags="AUTHORSHIP=Siemens /// CONNECTION_TYPES=axi4stream,clock,reset"
   categories="Verification/Simulation"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="my_elaborate" />
  <tag2
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  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="AXI4STREAM Slave BFM Reference Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/mentor_vip_axi4_stream_ae_usr.pdf" />
 </component>
 <plugin
   name="missing"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Missing"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
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 <plugin
   name="missing"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Missing Connection"
   version="1.0"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <component
   name="missing_module"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Missing Module"
   version="1.0"
   description="A Missing Module is added in place of a requested IP core when the requested IP is not found in the IP Catalog. "
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   factory="BeanElementFactory" />
 <component
   name="modular_sgdma_dispatcher"
   file="altera_msgdma/dispatcher/dispatcher_hw.tcl"
   displayName="Modular SGDMA Dispatcher IP"
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   description="SGDMA scheduling block"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,avalon_streaming,clock,interrupt /// INTERNAL_COMPONENT=false"
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   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate_me" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_me" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/lro1402196946061" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="multiplexer"
   file="avalon_st/altera_avalon_st_multiplexer/avalon-st_multiplexer_hw.tcl"
   displayName="Avalon-ST Multiplexer"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
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  <documentUrl
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     type="OTHER"
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 </component>
 <component
   name="native_10g_1588_312"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588_312.qsys"
   displayName="native_10g_1588_312"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588_312_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588_312_ls.qsys"
   displayName="native_10g_1588_312_ls"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588_322"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588_322.qsys"
   displayName="native_10g_1588_322"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588_322_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588_322_ls.qsys"
   displayName="native_10g_1588_322_ls"
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   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588_644"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588_644.qsys"
   displayName="native_10g_1588_644"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588_644_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588_644_ls.qsys"
   displayName="native_10g_1588_644_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588hp_312"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588hp_312.qsys"
   displayName="native_10g_1588hp_312"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588hp_312_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588hp_312_ls.qsys"
   displayName="native_10g_1588hp_312_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588hp_322"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588hp_322.qsys"
   displayName="native_10g_1588hp_322"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588hp_322_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588hp_322_ls.qsys"
   displayName="native_10g_1588hp_322_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588hp_644"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588hp_644.qsys"
   displayName="native_10g_1588hp_644"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_1588hp_644_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_1588hp_644_ls.qsys"
   displayName="native_10g_1588hp_644_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_322"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_322.qsys"
   displayName="native_10g_322"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_322_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_322_ls.qsys"
   displayName="native_10g_322_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_644"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_644.qsys"
   displayName="native_10g_644"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_644_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_644_ls.qsys"
   displayName="native_10g_644_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_fec_322"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_fec_322.qsys"
   displayName="native_10g_fec_322"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_fec_322_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_fec_322_ls.qsys"
   displayName="native_10g_fec_322_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_fec_644"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_fec_644.qsys"
   displayName="native_10g_fec_644"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_fec_644_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_fec_644_ls.qsys"
   displayName="native_10g_fec_644_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_fechp_322"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_fechp_322.qsys"
   displayName="native_10g_fechp_322"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_fechp_322_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_fechp_322_ls.qsys"
   displayName="native_10g_fechp_322_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_fechp_644"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_fechp_644.qsys"
   displayName="native_10g_fechp_644"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10g_fechp_644_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10g_fechp_644_ls.qsys"
   displayName="native_10g_fechp_644_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10ghp_322"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10ghp_322.qsys"
   displayName="native_10ghp_322"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10ghp_322_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10ghp_322_ls.qsys"
   displayName="native_10ghp_322_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10ghp_644"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10ghp_644.qsys"
   displayName="native_10ghp_644"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_10ghp_644_ls"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_10ghp_644_ls.qsys"
   displayName="native_10ghp_644_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_322"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_322.qsys"
   displayName="native_40g_322"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_322_ls"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_322_ls.qsys"
   displayName="native_40g_322_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_644"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_644.qsys"
   displayName="native_40g_644"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_644_ls"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_644_ls.qsys"
   displayName="native_40g_644_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_fec_322"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_fec_322.qsys"
   displayName="native_40g_fec_322"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_fec_322_ls"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_fec_322_ls.qsys"
   displayName="native_40g_fec_322_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_fec_644"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_fec_644.qsys"
   displayName="native_40g_fec_644"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_fec_644_ls"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_fec_644_ls.qsys"
   displayName="native_40g_fec_644_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_fechp_322"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_fechp_322.qsys"
   displayName="native_40g_fechp_322"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_fechp_322_ls"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_fechp_322_ls.qsys"
   displayName="native_40g_fechp_322_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_fechp_644"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_fechp_644.qsys"
   displayName="native_40g_fechp_644"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40g_fechp_644_ls"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40g_fechp_644_ls.qsys"
   displayName="native_40g_fechp_644_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40ghp_322"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40ghp_322.qsys"
   displayName="native_40ghp_322"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40ghp_322_ls"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40ghp_322_ls.qsys"
   displayName="native_40ghp_322_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40ghp_644"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40ghp_644.qsys"
   displayName="native_40ghp_644"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_40ghp_644_ls"
   file="ethernet/alt_eth_ultra/40g_kr4_a10/variants/native_40ghp_644_ls.qsys"
   displayName="native_40ghp_644_ls"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_gige"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_gige.qsys"
   displayName="native_gige"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="native_gige_1588"
   file="alt_xcvr/altera_xcvr_10gbase_kr/arria10/variants/native_gige_1588.qsys"
   displayName="native_gige_1588"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="nf_xcvr_10g_pll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE/rtl/pll_atxpll/nf_xcvr_10g_pll_a10.qsys"
   displayName="nf_xcvr_10g_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="nf_xcvr_10g_pll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/pll_atxpll/nf_xcvr_10g_pll_a10.qsys"
   displayName="nf_xcvr_10g_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="nf_xcvr_10g_pll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE/rtl/pll_atxpll/nf_xcvr_10g_pll_a10.qsys"
   displayName="nf_xcvr_10g_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="nf_xcvr_10g_pll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/pll_atxpll/nf_xcvr_10g_pll_a10.qsys"
   displayName="nf_xcvr_10g_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="nf_xcvr_1g_pll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE/rtl/pll_fpll/nf_xcvr_1g_pll_a10.qsys"
   displayName="nf_xcvr_1g_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="nf_xcvr_1g_pll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/pll_fpll/nf_xcvr_1g_pll_a10.qsys"
   displayName="nf_xcvr_1g_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="nf_xcvr_1g_pll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE/rtl/pll_fpll/nf_xcvr_1g_pll_a10.qsys"
   displayName="nf_xcvr_1g_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="nf_xcvr_1g_pll_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_LINESIDE_1588v2/rtl/pll_fpll/nf_xcvr_1g_pll_a10.qsys"
   displayName="nf_xcvr_1g_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="nios_custom_instruction"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="nios_custom_instruction"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="nios_custom_instruction"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Nios II Custom Instruction Connection"
   version="25.1"
   description="A connection to a Nios II custom instruction slave."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="nios_custom_instruction_master"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Custom Instruction Master"
   version="25.1"
   description="A processor can support Custom Instructions via a Custom Instruction Master."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="nios_custom_instruction_slave"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Custom Instruction Slave"
   version="25.1"
   description="A processor can support Custom Instructions via components with Custom Instruction slave interfaces."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="niosv_custom_instruction"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="niosv_custom_instruction"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="niosv_custom_instruction"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Nios V Custom Instruction Connection"
   version="25.1"
   description="A connection to a Nios V custom instruction subordinate."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="niosv_custom_instruction_manager"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Nios V Custom Instruction Manager"
   version="25.1"
   description="A processor can support Custom Instructions via a Nios V Custom Instruction Manager."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="niosv_custom_instruction_subordinate"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Nios V Custom Instruction Subordinate"
   version="25.1"
   description="A processor can support Custom Instructions via a Nios V Custom Instruction Subordinate."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <component
   name="oc_i2c_master"
   file="altera_dp/hw_demo/altera_avalon_i2c/oc_i2c_master_hw.tcl"
   displayName="oc_i2c_master"
   version="1.0"
   description=""
   tags="CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Bitec"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="oc_i2c_master"
   file="altera_dp/hw_demo/av_sk_4k/altera_avalon_i2c/oc_i2c_master_hw.tcl"
   displayName="oc_i2c_master"
   version="1.0"
   description=""
   tags="CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Bitec"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="oc_i2c_master"
   file="altera_dp/hw_demo/cv/altera_avalon_i2c/oc_i2c_master_hw.tcl"
   displayName="oc_i2c_master"
   version="1.0"
   description=""
   tags="CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Bitec"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="oc_i2c_master"
   file="altera_dp/hw_demo/mst_av_sk_4k/altera_avalon_i2c/oc_i2c_master_hw.tcl"
   displayName="oc_i2c_master"
   version="1.0"
   description=""
   tags="CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Bitec"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="oc_i2c_master"
   file="altera_dp/hw_demo/mst_sv/altera_avalon_i2c/oc_i2c_master_hw.tcl"
   displayName="oc_i2c_master"
   version="1.0"
   description=""
   tags="CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Bitec"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="oc_i2c_master"
   file="altera_dp/hw_demo/sv/altera_avalon_i2c/oc_i2c_master_hw.tcl"
   displayName="oc_i2c_master"
   version="1.0"
   description=""
   tags="CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Bitec"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="oc_i2c_master"
   file="altera_hdmi/hw_demo/arria_10/rtl/i2c_master/oc_i2c_master_hw.tcl"
   displayName="oc_i2c_master"
   version="1.0"
   description=""
   tags="AUTHORSHIP=Intel Corporation /// CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="default group"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
 </component>
 <component
   name="oc_i2c_master"
   file="altera_hdmi/hw_demo/av_sk_hdmi2/altera_avalon_i2c/oc_i2c_master_hw.tcl"
   displayName="oc_i2c_master"
   version="1.0"
   description=""
   tags="CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Bitec"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="oc_i2c_master"
   file="altera_hdmi/hw_demo/sv_hdmi2/altera_avalon_i2c/oc_i2c_master_hw.tcl"
   displayName="oc_i2c_master"
   version="1.0"
   description=""
   tags="CONNECTION_TYPES=avalon,clock,conduit,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories="Bitec"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="11.0" />
 </component>
 <component
   name="parallel_add"
   file="megafunctions/parallel_add/parallel_add_hw.tcl"
   displayName="PARALLEL_ADD"
   version="25.1"
   description="parallel_add"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Arithmetic"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_lpm_alt_mfug.pdf" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="pcie_cfbp_g1x1_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/qsys_example/pcie_cfbp_g1x1_ast64.qsys"
   displayName="pcie_cfbp_g1x1_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_cfbp_g1x8_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/qsys_example/pcie_cfbp_g1x8_ast64.qsys"
   displayName="pcie_cfbp_g1x8_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_cfbp_g2x4_ast128"
   file="altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/qsys_example/pcie_cfbp_g2x4_ast128.qsys"
   displayName="pcie_cfbp_g2x4_ast128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_cfbp_g2x8_ast128"
   file="altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/qsys_example/pcie_cfbp_g2x8_ast128.qsys"
   displayName="pcie_cfbp_g2x8_ast128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_cfbp_g2x8_ast256"
   file="altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/qsys_example/pcie_cfbp_g2x8_ast256.qsys"
   displayName="pcie_cfbp_g2x8_ast256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_cfbp_g3x8_ast256"
   file="altera_pcie/altera_pcie_hip_ast_ed/altera_pcie_cfgbp_ed/qsys_example/pcie_cfbp_g3x8_ast256.qsys"
   displayName="pcie_cfbp_g3x8_ast256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_ep_dma_g1x8_av_integrated"
   file="altera_pcie/altera_pcie_hip_256_avmm/example_design/av/pcie_de_ep_dma_g1x8_av_integrated.qsys"
   displayName="pcie_de_ep_dma_g1x8_av_integrated"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_ep_dma_g2x4_cv"
   file="altera_pcie/altera_pcie_hip_256_avmm/example_design/cv/pcie_de_ep_dma_g2x4_cv.qsys"
   displayName="pcie_de_ep_dma_g2x4_cv"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_ep_dma_g3x8"
   file="altera_pcie/altera_pcie_hip_256_avmm/example_design/sv/pcie_de_ep_dma_g3x8.qsys"
   displayName="pcie_de_ep_dma_g3x8"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_ep_dma_g3x8_integrated"
   file="altera_pcie/altera_pcie_hip_256_avmm/example_design/sv/pcie_de_ep_dma_g3x8_integrated.qsys"
   displayName="pcie_de_ep_dma_g3x8_integrated"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen1_x1_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/cv/pcie_de_gen1_x1_ast64.qsys"
   displayName="pcie_de_gen1_x1_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen1_x2_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/av/pcie_de_gen1_x2_ast64.qsys"
   displayName="pcie_de_gen1_x2_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen1_x4_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/av/pcie_de_gen1_x4_ast64.qsys"
   displayName="pcie_de_gen1_x4_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen1_x4_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/avgz/pcie_de_gen1_x4_ast64.qsys"
   displayName="pcie_de_gen1_x4_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen1_x4_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/cv/pcie_de_gen1_x4_ast64.qsys"
   displayName="pcie_de_gen1_x4_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen1_x4_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/sv/pcie_de_gen1_x4_ast64.qsys"
   displayName="pcie_de_gen1_x4_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen1_x8_ast128"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/av/pcie_de_gen1_x8_ast128.qsys"
   displayName="pcie_de_gen1_x8_ast128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen1_x8_ast128"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/avgz/pcie_de_gen1_x8_ast128.qsys"
   displayName="pcie_de_gen1_x8_ast128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen1_x8_ast128"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/sv/pcie_de_gen1_x8_ast128.qsys"
   displayName="pcie_de_gen1_x8_ast128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen2_x8_ast256"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/avgz/pcie_de_gen2_x8_ast256.qsys"
   displayName="pcie_de_gen2_x8_ast256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen2_x8_ast256"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/sv/pcie_de_gen2_x8_ast256.qsys"
   displayName="pcie_de_gen2_x8_ast256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen3_x1_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/avgz/pcie_de_gen3_x1_ast64.qsys"
   displayName="pcie_de_gen3_x1_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen3_x1_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/sv/pcie_de_gen3_x1_ast64.qsys"
   displayName="pcie_de_gen3_x1_ast64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen3_x4_ast128"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/avgz/pcie_de_gen3_x4_ast128.qsys"
   displayName="pcie_de_gen3_x4_ast128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen3_x4_ast128"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/sv/pcie_de_gen3_x4_ast128.qsys"
   displayName="pcie_de_gen3_x4_ast128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen3_x8_ast256"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/avgz/pcie_de_gen3_x8_ast256.qsys"
   displayName="pcie_de_gen3_x8_ast256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_gen3_x8_ast256"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/sv/pcie_de_gen3_x8_ast256.qsys"
   displayName="pcie_de_gen3_x8_ast256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="pcie_de_rp_gen1_x4_ast64"
   file="altera_pcie/altera_pcie_hip_ast_ed/example_design/av/pcie_de_rp_gen1_x4_ast64.qsys"
   displayName="pcie_de_rp_gen1_x4_ast64"
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   displayName="64b or 128b PIO AVST "
   version="25.1"
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 <component
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 <component
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 <component
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 <component
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 <component
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   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE_1588v2/rtl/pll_mpll/pll_2_a10.qsys"
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 <component
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 <component
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   displayName="pll_a10"
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 <component
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   file="ethernet/alt_em10g32/example_design/LL10G_1G_10G_LINESIDE/rtl/pll_mpll/pll_a10.qsys"
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 <component
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 <component
   name="pll_hdmi"
   file="altera_hdmi/hw_demo/arria_10/rtl/pll/pll_hdmi.qsys"
   displayName="pll_hdmi"
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   description=""
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 </component>
 <component
   name="pll_hdmi_reconfig"
   file="altera_hdmi/hw_demo/arria_10/rtl/pll/pll_hdmi_reconfig.qsys"
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 <component
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 </component>
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 <component
   name="qsys_interface_bridge"
   file="altera_lvds/top/ex_design/qsys_interface_bridge/qsys_interface_bridge_hw.tcl"
   displayName="qsys_interface_bridge"
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 </component>
 <component
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   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
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 </component>
 <component
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   file="altera_hdmi/hw_demo/av_sk/qsys_vip_passthrough.qsys"
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 </component>
 <component
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   file="altera_hdmi/hw_demo/av_sk_hdmi2/qsys_vip_passthrough.qsys"
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 </component>
 <component
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   file="altera_hdmi/hw_demo/sv_hdmi2/qsys_vip_passthrough.qsys"
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 </component>
 <component
   name="ram_1port"
   file="megafunctions/ram_1port/ram_1_port_hw.tcl"
   displayName="RAM: 1-PORT Intel FPGA IP"
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   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/On Chip Memory"
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  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
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     displayName="User Guide"
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     displayName="Release Notes"
     type="OTHER"
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 </component>
 <component
   name="ram_2port"
   file="megafunctions/ram_2port/ram_2_port_hw.tcl"
   displayName="RAM: 2-PORT Intel FPGA IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
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  <documentUrl
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     url="https://documentation.altera.com/#/link/eis1413425716965/eis1413185370899" />
  <documentUrl
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     type="OTHER"
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 </component>
 <component
   name="ram_4port"
   file="megafunctions/ram_4port/ram_4_port_hw.tcl"
   displayName="RAM: 4-PORT"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
     displayName="Data Sheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_ram_rom.pdf" />
 </component>
 <component
   name="rddc_mc_256b"
   file="altera_pcie/altera_pcie_hip_256_avmm/channelizer/example_design/rddc_mc_256b.qsys"
   displayName="rddc_mc_256b"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="reset"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="reset"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="reset"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Reset Connection"
   version="25.1"
   description="A reset connection."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="reset_adaptation_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="Reset Adaptation Transform"
   version="25.1"
   description="Inserts reset controllers where necessary for merging and synchronization"
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
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 <component
   name="reset_control_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER/rtl/xcvr_reset_controller/reset_control_a10.qsys"
   displayName="reset_control_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="reset_control_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER_RegMode/rtl/xcvr_reset_controller/reset_control_a10.qsys"
   displayName="reset_control_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="reset_controller"
   file="altera_hdmi/hw_demo/arria_10/rtl/common/reset_controller.qsys"
   displayName="reset_controller"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="reset_sink"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Reset Input"
   version="25.1"
   description="A rest input interface provides reset control for a component."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="reset_source"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Reset Output"
   version="25.1"
   description="A reset output interface drives a reset signal out of a component."
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
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 <plugin
   name="reset_upgrade_transform"
   file="dsp/lib/helpers/com.altera.sopcmodel.transforms.jar"
   displayName="Reset Upgrade Transform"
   version="25.1"
   description="Connects all reset sinks to all reset sources"
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.sopcmodel.transforms.interfaces.ITransformStep"
   factory="BeanElementFactory" />
 <plugin
   name="rld3.qprs"
   file="emif/hwtcl/altera_emif/rld3.qprs"
   displayName="rld3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif" />
 </plugin>
 <plugin
   name="rld3.qprs"
   file="emif/hwtcl/altera_emif_s10/rld3.qprs"
   displayName="rld3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_emif_s10" />
 </plugin>
 <plugin
   name="rld3.qprs"
   file="emif/ip_top/presets/rld3.qprs"
   displayName="rld3.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="ip_top" />
 </plugin>
 <plugin
   name="rld3_devkit.qprs"
   file="emif/hwtcl/altera_emif/rld3_devkit.qprs"
   displayName="rld3_devkit.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
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 </plugin>
 <plugin
   name="rld3_devkit.qprs"
   file="emif/ip_top/presets/rld3_devkit.qprs"
   displayName="rld3_devkit.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="ip_top" />
 </plugin>
 <component
   name="rom_1port"
   file="megafunctions/rom_1port/rom_1_port_hw.tcl"
   displayName="ROM: 1-PORT Intel FPGA IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10 /// Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.0" />
  <documentUrl
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  <documentUrl
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  <documentUrl
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     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="rom_2port"
   file="megafunctions/rom_2port/rom_2_port_hw.tcl"
   displayName="ROM: 2-PORT Intel FPGA IP"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/On Chip Memory"
   factory="TclModuleFactory">
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 </component>
 <component
   name="rp_g1x1_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g1x1_avmm64.qsys"
   displayName="rp_g1x1_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g1x1_avmm64_625"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g1x1_avmm64_625.qsys"
   displayName="rp_g1x1_avmm64_625"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g1x2_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g1x2_avmm64.qsys"
   displayName="rp_g1x2_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g1x4"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g1x4.qsys"
   displayName="rp_g1x4"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g1x4_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g1x4_avmm64.qsys"
   displayName="rp_g1x4_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g1x8"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g1x8.qsys"
   displayName="rp_g1x8"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g1x8_avmm128"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g1x8_avmm128.qsys"
   displayName="rp_g1x8_avmm128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g1x8_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g1x8_avmm64.qsys"
   displayName="rp_g1x8_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g2x1_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g2x1_avmm64.qsys"
   displayName="rp_g2x1_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g2x2_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g2x2_avmm64.qsys"
   displayName="rp_g2x2_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g2x4_avmm128"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g2x4_avmm128.qsys"
   displayName="rp_g2x4_avmm128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g2x4_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g2x4_avmm64.qsys"
   displayName="rp_g2x4_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g2x8_avmm128"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g2x8_avmm128.qsys"
   displayName="rp_g2x8_avmm128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g2x8_avmm256"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g2x8_avmm256.qsys"
   displayName="rp_g2x8_avmm256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g3x1_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g3x1_avmm64.qsys"
   displayName="rp_g3x1_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g3x2_avmm128"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g3x2_avmm128.qsys"
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   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g3x2_avmm64"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g3x2_avmm64.qsys"
   displayName="rp_g3x2_avmm64"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g3x4_avmm128"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g3x4_avmm128.qsys"
   displayName="rp_g3x4_avmm128"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g3x4_avmm256"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g3x4_avmm256.qsys"
   displayName="rp_g3x4_avmm256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rp_g3x8_avmm256"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/rp_g3x8_avmm256.qsys"
   displayName="rp_g3x8_avmm256"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rsdec"
   file="ethernet/alt_e2550/25g_rsfec/rsdec.qsys"
   displayName="rsdec"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="rsenc"
   file="ethernet/alt_e2550/25g_rsfec/rsenc.qsys"
   displayName="rsenc"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="s10_ast2avmm_bridge_256"
   file="altera_pcie/altera_pcie_s10_ed/ast2avmm_bridge_256/ast2avmm_bridge_256_hw.tcl"
   displayName="Stratix 10 256 Bits AST2AVMM Bridge"
   version="25.1"
   description="256 Bits AST to AVMM Bridge with Burst RX Master, TX Slave and CRA Interfaces"
   tags="AUTHORSHIP=Altera /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/PCI Express/QSYS Example Designs"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.1" />
 </component>
 <component
   name="sc_fifo_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER/rtl/fifo_scfifo/sc_fifo_a10.qsys"
   displayName="sc_fifo_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="sc_fifo_a10"
   file="ethernet/alt_em10g32/example_design/LL10G_10GBASER_RegMode/rtl/fifo_scfifo/sc_fifo_a10.qsys"
   displayName="sc_fifo_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="scu"
   file="hps/hard_peripheral_logical_view/scu/scu_hw.tcl"
   displayName="ARM Snoop Control Unit"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="sdi_ii"
   file="sdi_ii/sdi_ii/sdi_ii_hw.tcl"
   displayName="SDI II Intel FPGA IP"
   version="25.1"
   description="SDI II"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=false"
   categories="Interface Protocols/Audio &amp; Video"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="parameter_upgrade_callback" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Stratix V /// Arria V GZ /// Arria V /// Cyclone V /// Arria 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="EXAMPLE_DESIGN" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validate_callback" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/bhc1410937441525.html" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/hco1421697949076.html" />
  <documentUrl
     displayName="Design Example User Guide for Intel Arria 10"
     type="OTHER"
     url="https://www.intel.com/content/www/us/en/programmable/documentation/smx1471929114447.html" />
 </component>
 <component
   name="sdi_ii_ed_loopback"
   file="sdi_ii/sdi_ii_ed_loopback/sdi_ii_ed_loopback_hw.tcl"
   displayName="SDI II ED Loopback"
   version="25.1"
   description="SDI II ED Loopback"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II/SDI II ED Loopback"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_ed_reconfig_a10"
   file="sdi_ii/sdi_ii_ed_reconfig_a10/sdi_ii_ed_reconfig_a10_hw.tcl"
   displayName="SDI II Reconfig Arria 10"
   version="25.1"
   description="SDI II Reconfig Arria 10"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II Reconfig Arria 10"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_ed_reconfig_mgmt"
   file="sdi_ii/sdi_ii_ed_reconfig_mgmt/sdi_ii_ed_reconfig_mgmt_hw.tcl"
   displayName="SDI II Reconfig Management"
   version="25.1"
   description="SDI II Reconfig Management"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II Reconfig Mgmt"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_ed_reconfig_router"
   file="sdi_ii/sdi_ii_ed_reconfig_router/sdi_ii_ed_reconfig_router_hw.tcl"
   displayName="SDI II Reconfig Router"
   version="25.1"
   description="SDI II Reconfig Router"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II Reconfig Router"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_ed_vid_pattgen"
   file="sdi_ii/sdi_ii_ed_vid_pattgen/sdi_ii_ed_vid_pattgen_hw.tcl"
   displayName="SDI II Video Pattern Generator"
   version="25.1"
   description="SDI II Video Pattern Generator"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II Video Pattern Generator"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_example_design"
   file="sdi_ii/sdi_ii_example_design/composed_ed/sdi_ii_example_design_hw.tcl"
   displayName="SDI II Example Design"
   version="25.1"
   description="SDI II Example Design"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II Example Design"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_phy_adapter"
   file="sdi_ii/sdi_ii_library/sdi_ii_phy_adapter/sdi_ii_phy_adapter_hw.tcl"
   displayName="SDI II PHY ADAPTER"
   version="25.1"
   description="SDI II PHY Adapter"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II/SDI II PHY Adapter"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_rx_phy_mgmt"
   file="sdi_ii/sdi_ii_library/sdi_ii_rx_phy_mgmt/sdi_ii_rx_phy_mgmt_hw.tcl"
   displayName="SDI II RX PHY Management"
   version="25.1"
   description="SDI II RX PHY Management"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II/SDI II RX PHY Management"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_rx_protocol"
   file="sdi_ii/sdi_ii_library/sdi_ii_rx_protocol/sdi_ii_rx_protocol_hw.tcl"
   displayName="SDI II RX Protocol"
   version="25.1"
   description="SDI II RX Protocol"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II/SDI II RX Protocol"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_tb"
   file="sdi_ii/sdi_ii_tb/sdi_ii_tb_hw.tcl"
   displayName="SDI II Testbench"
   version="25.1"
   description="SDI II Testbench"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II Testbench"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="compose_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_tb_control"
   file="sdi_ii/sdi_ii_tb_control/sdi_ii_tb_control_hw.tcl"
   displayName="SDI II Testbench Control"
   version="25.1"
   description="SDI II Testbench Control"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II Testbench Control"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_tb_rx_checker"
   file="sdi_ii/sdi_ii_tb_rx_checker/sdi_ii_tb_rx_checker_hw.tcl"
   displayName="SDI II Testbench Receiver Checker"
   version="25.1"
   description="SDI II Testbench Receiver Checker"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II Testbench Receiver Checker"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_tb_tx_checker"
   file="sdi_ii/sdi_ii_tb_tx_checker/sdi_ii_tb_tx_checker_hw.tcl"
   displayName="SDI II Testbench Tx Checker"
   version="25.1"
   description="SDI II Testbench Tx Checker"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II Testbench Tx Checker"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_tx_phy_mgmt"
   file="sdi_ii/sdi_ii_library/sdi_ii_tx_phy_mgmt/sdi_ii_tx_phy_mgmt_hw.tcl"
   displayName="SDI II TX PHY Management"
   version="25.1"
   description="SDI II TX PHY Management"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II/SDI II TX PHY Management"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdi_ii_tx_protocol"
   file="sdi_ii/sdi_ii_library/sdi_ii_tx_protocol/sdi_ii_tx_protocol_hw.tcl"
   displayName="SDI II TX Protocol"
   version="25.1"
   description="SDI II TX Protocol"
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/SDI II/SDI II TX Protocol"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
 </component>
 <component
   name="sdmmc"
   file="hps/hard_peripheral_logical_view/sdmmc/sdmmc_hw.tcl"
   displayName="Synopsys SDMMC"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="seq_sim_apb_bfm"
   file="alt_mem_if/altera_mem_if_qseq/seq_sim_apb_bfm/seq_sim_apb_bfm_hw.tcl"
   displayName="UniPHY Sequencer APB Master BFM"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VERILOG,SIM_VHDL,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="seq_sim_bfm"
   file="alt_mem_if/altera_mem_if_qseq/seq_sim_bfm/seq_sim_bfm_hw.tcl"
   displayName="seq_sim_bfm"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="sequencer_data_mgr_110"
   file="alt_mem_if/altera_mem_if_qseq/data_mgr_110/sequencer_data_mgr_hw.tcl"
   displayName="UniPHY Data Manager (11.0 Version)"
   version="25.1"
   description="Data Manager"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_m10"
   file="alt_mem_if/altera_mem_if_qseq/m10_rtl_seq/sequencer_m10_hw.tcl"
   displayName="UniPHY Max10 RTL sequencer"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_phy_mgr_100"
   file="alt_mem_if/altera_mem_if_qseq/phy_mgr_100/sequencer_phy_mgr_hw.tcl"
   displayName="UniPHY PHY Manager (10.0 Version)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_pll_mgr_140"
   file="alt_mem_if/altera_mem_if_qseq/pll_mgr_140/sequencer_pll_mgr_hw.tcl"
   displayName="UniPHY PLL Manager (14.0 Version)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_ptr_mgr_100"
   file="alt_mem_if/altera_mem_if_qseq/ptr_mgr_100/sequencer_ptr_mgr_hw.tcl"
   displayName="UniPHY Pointer Manager (10.0 Version)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_reg_file_111"
   file="alt_mem_if/altera_mem_if_qseq/reg_file_111/sequencer_reg_file_hw.tcl"
   displayName="UniPHY Register File (11.1 Version)"
   version="25.1"
   description="Register File (11.1)"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_rw_mgr_ddr2_110"
   file="alt_mem_if/altera_mem_if_qseq/rw_mgr_110/rw_manager_ddr2_hw.tcl"
   displayName="UniPHY DDR2 Read/Write Manager (11.0 Version)"
   version="25.1"
   description="RW Manager DDR2 (11.0)"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_rw_mgr_ddr3_110"
   file="alt_mem_if/altera_mem_if_qseq/rw_mgr_110/rw_manager_ddr3_hw.tcl"
   displayName="UniPHY DDR3 Read/Write Manager (11.0 Version)"
   version="25.1"
   description="RW Manager DDR3 (11.0)"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_rw_mgr_lpddr2_110"
   file="alt_mem_if/altera_mem_if_qseq/rw_mgr_110/rw_manager_lpddr2_hw.tcl"
   displayName="UniPHY LPDDR2 Read/Write Manager (11.0 Version)"
   version="25.1"
   description="RW Manager LPDDR2 (11.0)"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_rw_mgr_lpddr_111"
   file="alt_mem_if/altera_mem_if_qseq/rw_mgr_110/rw_manager_lpddr_hw.tcl"
   displayName="UniPHY LPDDR Read/Write Manager (11.1 Version)"
   version="25.1"
   description="RW Manager LPDDR (11.1)"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_rw_mgr_qdrii_110"
   file="alt_mem_if/altera_mem_if_qseq/rw_mgr_110/rw_manager_qdrii_hw.tcl"
   displayName="UniPHY QDRII Read/Write Manager (11.0 Version)"
   version="25.1"
   description="RW Manager QDRII (11.0)"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_rw_mgr_rldram3_110"
   file="alt_mem_if/altera_mem_if_qseq/rw_mgr_110/rw_manager_rldram3_hw.tcl"
   displayName="UniPHY RLDRAM 3 Read/Write Manager (11.0 Version)"
   version="25.1"
   description="RW Manager RLDRAM 3 (11.0)"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_rw_mgr_rldram_110"
   file="alt_mem_if/altera_mem_if_qseq/rw_mgr_110/rw_manager_rldram_hw.tcl"
   displayName="UniPHY RLDRAM Read/Write Manager (11.0 Version)"
   version="25.1"
   description="RW Manager RLDRAM (11.0)"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_scc_mgr_100"
   file="alt_mem_if/altera_mem_if_qseq/scc_mgr_100/sequencer_scc_mgr_hw.tcl"
   displayName="UniPHY Scan Chain Manager (10.0 Version)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_scc_mgr_110"
   file="alt_mem_if/altera_mem_if_qseq/scc_mgr_110/sequencer_scc_mgr_hw.tcl"
   displayName="UniPHY Scan Chain Manager (10.0 Version)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_timer_120"
   file="alt_mem_if/altera_mem_if_qseq/seq_timer_120/sequencer_timer_hw.tcl"
   displayName="UniPHY Sequencer Timer (12.0 Version)"
   version="25.1"
   description="Sequencer Timer (12.0)"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="sequencer_trk_mgr"
   file="alt_mem_if/altera_mem_if_qseq/trk_mgr_110/sequencer_trk_mgr_hw.tcl"
   displayName="UniPHY Tracking Manager"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Memory Interfaces and Controllers/Memory Interfaces with UniPHY/Internal Components/Memory Sequencer Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
 </component>
 <component
   name="seriallite_iii_a10"
   file="seriallite_iii/src/seriallite_iii_a10_hw.tcl"
   displayName="Serial Lite III Streaming Arria 10 IP"
   version="25.1"
   description="seriallite_iii_a10_top"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Interface Protocols/SerialLite"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Arria 10" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,EXAMPLE_DESIGN,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
  <documentUrl
     displayName="Datasheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_slite3_streaming.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411113020049/bhc1411112778182" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697961295" />
  <documentUrl
     displayName="Example Design User Guide"
     type="OTHER"
     url="https://www.altera.com/documentation/bhc1411113011076.html" />
 </component>
 <component
   name="seriallite_iii_sv"
   file="seriallite_iii/src/seriallite_iii_sv_hw.tcl"
   displayName="Serial Lite III Streaming IP"
   version="25.1"
   description="seriallite_iii_sv_top"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Interface Protocols/SerialLite"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix V /// Arria V GZ" />
  <tag2
     key="SUPPORTED_FILE_SETS"
     value="QUARTUS_SYNTH,EXAMPLE_DESIGN,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2 key="VALIDATION_CALLBACK" value="validation_callback" />
  <documentUrl
     displayName="Datasheet"
     type="OTHER"
     url="http://www.altera.com/literature/ug/ug_slite3_streaming.pdf" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411113020049/bhc1411112778182" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697961295" />
  <documentUrl
     displayName="Example Design User Guide"
     type="OTHER"
     url="https://www.altera.com/documentation/ylx1497333748890.html" />
 </component>
 <component
   name="simple_1mm_traffic_gen_core"
   file="alt_mem_if/altera_avalon_mm_traffic_generator/simple_1mm_traffic_gen_core/simple_1mm_traffic_gen_core_hw.tcl"
   displayName="Simple 1-Port Traffic Generator and BIST Engine Core"
   version="25.1"
   description="Simple 1-Port Traffic Generator and BIST Engine Core"
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Simulation; Debug and Verification/Verification/Internal Components/Pattern Generator Components"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="true" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="ip_elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="ip_validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/lit-external-memory-interface.jsp" />
 </component>
 <component
   name="snps_uart"
   file="hps/hard_peripheral_logical_view/snps_uart/snps_uart_hw.tcl"
   displayName="Synopsys UART"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="soft_asmiblock"
   file="generic_qspi_controller/soft_asmiblock_hw.tcl"
   displayName="SOFT ASMIBLOCK"
   version="25.1"
   description="This component connects to Altera EPCQ controller so that the QSPI signal can be used as general purpose pin"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=conduit /// INTERNAL_COMPONENT=true"
   categories="Basic Functions/Configuration and Programming"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="REPORT_HIERARCHY" value="false" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG" />
  <tag2 key="TCL_PACKAGE_VERSION" value="14.1" />
 </component>
 <component
   name="spi"
   file="hps/hard_peripheral_logical_view/spi/spi_hw.tcl"
   displayName="Synopsys SPI"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="spi_slave_to_avalon_mm_master_bridge"
   file="sopc_builder_ip/altera_avalon_spislave_to_avalonmm_bridge/SPISlaveToAvalonMasterBridge_hw.tcl"
   displayName="SPI Slave to Avalon Master Bridge IP"
   version="25.1"
   description="SPI Slave To Avalon Master Bridge is a collection of pre-wired components that provide an Avalon Master using an external SPI interface "
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon,clock,conduit"
   categories="Processors and Peripherals/Peripherals"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401396548170" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="spislave"
   file="sopc_builder_ip/altera_avalon_spi_phy_slave/spiphyslave_hw.tcl"
   displayName="Avalon-ST Serial Peripheral Interface (SPI) IP"
   version="25.1"
   description="SPI to Avalon ST Bridge"
   tags="AUTHORSHIP=Altera /// CONNECTION_TYPES=avalon_streaming,clock,conduit"
   categories="Interface Protocols/Serial"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/sfo1400787952932/iga1401395000089" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="sriov2_target_g3x8_1pf_4vf"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/sriov2_target_g3x8_1pf_4vf.qsys"
   displayName="sriov2_target_g3x8_1pf_4vf"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="sriov_mcdma_app_g3x8_256b"
   file="altera_pcie/altera_pcie_hip_256_avmm/channelizer/example_design/sriov_mcdma_app_g3x8_256b.qsys"
   displayName="sriov_mcdma_app_g3x8_256b"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="sriov_top_target_gen2_x8_256b_2pf"
   file="altera_pcie/altera_pcie_sriov/example_design/sriov_top_target_gen2_x8_256b_2pf.qsys"
   displayName="sriov_top_target_gen2_x8_256b_2pf"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="sriov_top_target_gen3_x8_256b_1pf_32vf"
   file="altera_pcie/altera_pcie_sriov/example_design/sriov_top_target_gen3_x8_256b_1pf_32vf.qsys"
   displayName="sriov_top_target_gen3_x8_256b_1pf_32vf"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="sriov_top_target_gen3_x8_256b_2pf_0vf_64vf"
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   displayName="sriov_top_target_gen3_x8_256b_2pf_0vf_64vf"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="sriov_top_target_gen3_x8_256b_2pf_128vf"
   file="altera_pcie/altera_pcie_a10_ed/example_design/a10/sriov_top_target_gen3_x8_256b_2pf_128vf.qsys"
   displayName="sriov_top_target_gen3_x8_256b_2pf_128vf"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="sriov_top_target_gen3_x8_256b_2pf_128vf"
   file="altera_pcie/altera_pcie_sriov/example_design/sriov_top_target_gen3_x8_256b_2pf_128vf.qsys"
   displayName="sriov_top_target_gen3_x8_256b_2pf_128vf"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="sriov_top_target_gen3_x8_256b_2pf_32vf_0vf"
   file="altera_pcie/altera_pcie_sriov/example_design/sriov_top_target_gen3_x8_256b_2pf_32vf_0vf.qsys"
   displayName="sriov_top_target_gen3_x8_256b_2pf_32vf_0vf"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="sriov_top_target_gen3_x8_256b_2pf_4vf"
   file="altera_pcie/altera_pcie_sriov/example_design/sriov_top_target_gen3_x8_256b_2pf_4vf.qsys"
   displayName="sriov_top_target_gen3_x8_256b_2pf_4vf"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="stmmac"
   file="hps/hard_peripheral_logical_view/stmmac/stmmac_hw.tcl"
   displayName="Synopsys GMAC"
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   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="stratix10_arm_gic"
   file="altera_hps/s10/gic/arm_gic_hw.tcl"
   displayName="ARM GIC"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="stratix10_axi_ocram"
   file="altera_hps/s10/device_tree_generation/axi_ocram_hw.tcl"
   displayName="HPS On Chip RAM"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="stratix10_clkctrl"
   file="megafunctions/stratix10_clkctrl/stratix10_clkctrl_hw.tcl"
   displayName="Stratix 10 Clock Control"
   version="25.1"
   description="&lt;html&gt;Allows signals to use the clock network in the device.&lt;/html&gt;"
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Clocks; PLLs and Resets"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elab" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="parameter_upgrade_callback" />
  <tag2 key="SUPPORTED_DEVICE_FAMILIES" value="Stratix 10" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.0" />
  <tag2
     key="UPGRADEABLE_FROM"
     value="altclkctrl/13.0/Arria 10 /// altclkctrl/13.0/Stratix V /// altclkctrl/13.0/Arria V /// altclkctrl/13.0/Arria V GZ /// altclkctrl/13.0/Cyclone V /// altclkctrl/13.0/MAX 10 FPGA /// altclkctrl/13.0/Cyclone IV E /// altclkctrl/13.0/Cyclone IV GX /// altclkctrl/13.0/Stratix IV /// altclkctrl/13.1/Arria 10 /// altclkctrl/13.1/Stratix V /// altclkctrl/13.1/Arria V /// altclkctrl/13.1/Arria V GZ /// altclkctrl/13.1/Cyclone V /// altclkctrl/13.1/MAX 10 FPGA /// altclkctrl/13.1/Cyclone IV E /// altclkctrl/13.1/Cyclone IV GX /// altclkctrl/13.1/Stratix IV /// altclkctrl/14.0/Arria 10 /// altclkctrl/14.0/Stratix V /// altclkctrl/14.0/Arria V /// altclkctrl/14.0/Arria V GZ /// altclkctrl/14.0/Cyclone V /// altclkctrl/14.0/MAX 10 FPGA /// altclkctrl/14.0/Cyclone IV E /// altclkctrl/14.0/Cyclone IV GX /// altclkctrl/14.0/Stratix IV /// altclkctrl/14.1/Arria 10 /// altclkctrl/14.1/Stratix V /// altclkctrl/14.1/Arria V /// altclkctrl/14.1/Arria V GZ /// altclkctrl/14.1/Cyclone V /// altclkctrl/14.1/MAX 10 FPGA /// altclkctrl/14.1/Cyclone IV E /// altclkctrl/14.1/Cyclone IV GX /// altclkctrl/14.1/Stratix IV /// altclkctrl/15.0/Arria 10 /// altclkctrl/15.0/Stratix V /// altclkctrl/15.0/Arria V /// altclkctrl/15.0/Arria V GZ /// altclkctrl/15.0/Cyclone V /// altclkctrl/15.0/MAX 10 FPGA /// altclkctrl/15.0/Cyclone IV E /// altclkctrl/15.0/Cyclone IV GX /// altclkctrl/15.0/Stratix IV /// altclkctrl/15.1/Arria 10 /// altclkctrl/15.1/Stratix V /// altclkctrl/15.1/Arria V /// altclkctrl/15.1/Arria V GZ /// altclkctrl/15.1/Cyclone V /// altclkctrl/15.1/MAX 10 FPGA /// altclkctrl/15.1/Cyclone IV E /// altclkctrl/15.1/Cyclone IV GX /// altclkctrl/15.1/Stratix IV /// altclkctrl/16.0,/Arria 10 /// altclkctrl/16.0,/Stratix V /// altclkctrl/16.0,/Arria V /// altclkctrl/16.0,/Arria V GZ /// altclkctrl/16.0,/Cyclone V /// altclkctrl/16.0,/MAX 10 FPGA /// altclkctrl/16.0,/Cyclone IV E /// altclkctrl/16.0,/Cyclone IV GX /// altclkctrl/16.0,/Stratix IV /// altclkctrl/16.1,/Arria 10 /// altclkctrl/16.1,/Stratix V /// altclkctrl/16.1,/Arria V /// altclkctrl/16.1,/Arria V GZ /// altclkctrl/16.1,/Cyclone V /// altclkctrl/16.1,/MAX 10 FPGA /// altclkctrl/16.1,/Cyclone IV E /// altclkctrl/16.1,/Cyclone IV GX /// altclkctrl/16.1,/Stratix IV /// altclkctrl/17.0,/Arria 10 /// altclkctrl/17.0,/Stratix V /// altclkctrl/17.0,/Arria V /// altclkctrl/17.0,/Arria V GZ /// altclkctrl/17.0,/Cyclone V /// altclkctrl/17.0,/MAX 10 FPGA /// altclkctrl/17.0,/Cyclone IV E /// altclkctrl/17.0,/Cyclone IV GX /// altclkctrl/17.0,/Stratix IV /// altclkctrl/17.1/Arria 10 /// altclkctrl/17.1/Stratix V /// altclkctrl/17.1/Arria V /// altclkctrl/17.1/Arria V GZ /// altclkctrl/17.1/Cyclone V /// altclkctrl/17.1/MAX 10 FPGA /// altclkctrl/17.1/Cyclone IV E /// altclkctrl/17.1/Cyclone IV GX /// altclkctrl/17.1/Stratix IV" />
 </component>
 <component
   name="stratix10_hps_bridge_avalon"
   file="altera_hps/s10/hps_bridge_avalon/hps_bridge_avalon_hw.tcl"
   displayName="HPS Bridge Avalon"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="stratix10_timer"
   file="altera_hps/s10/device_tree_generation/timer_hw.tcl"
   displayName="ARM internal timer"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="15.0" />
 </component>
 <component
   name="sv_xcvr_custom"
   file="altera_xcvr_8g_custom/sv/sv_xcvr_custom_hw.tcl"
   displayName="Stratix V Custom Native PHY"
   version="25.1"
   description="Standard Transceiver PCS Stratix V Custom Native PHY IP"
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="validate" />
  <documentUrl
     displayName="DATASHEET"
     type="DATASHEET"
     url="http://www.altera.com/literature/ug/xcvr_user_guide.pdf" />
 </component>
 <component
   name="sv_xcvr_pipe_native"
   file="altera_pcie_pipe/sv/sv_xcvr_pipe_native_hw.tcl"
   displayName="Stratix V Native PHY for PCI Express (PIPE)"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/PCI"
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="true" />
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="ELABORATION_CALLBACK" value="elaboration_callback" />
  <tag2 key="SUPPORTED_FILE_SETS" value="SIM_VHDL,SIM_VERILOG,QUARTUS_SYNTH" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
  <tag2 key="VALIDATION_CALLBACK" value="my_validation_callback" />
 </component>
 <component
   name="sv_xcvr_reconfig_basic"
   file="alt_xcvr_reconfig/alt_xcvr_reconfig_basic/sv_xcvr_reconfig_basic_hw.tcl"
   displayName="Stratix V Transceiver Reconfiguration Basic Interface Block"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation /// CONNECTION_TYPES=clock,conduit,reset /// INTERNAL_COMPONENT=true"
   categories="Interface Protocols/Transceiver PHY"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="true" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="10.1" />
 </component>
 <component
   name="testbench"
   file="vip/verification/testbench/testbench.qsys"
   displayName="testbench"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="timing_adapter"
   file="avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl"
   displayName="Avalon-ST Timing Adapter"
   version="25.1"
   description=""
   tags="AUTHORSHIP=Altera Corporation"
   categories="Basic Functions/Bridges and Adaptors/Streaming"
   factory="TclModuleFactory">
  <tag2 key="ANALYZE_HDL" value="false" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="PARAMETER_UPGRADE_CALLBACK" value="upgrade" />
  <tag2 key="SUPPORTED_FILE_SETS" value="QUARTUS_SYNTH,SIM_VERILOG,SIM_VHDL" />
  <tag2 key="TCL_PACKAGE_VERSION" value="13.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/mwh1409960181641/mwh1409958828732" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421698013408" />
 </component>
 <component
   name="top"
   file="altera_pcie/altera_pcie_hip_256_avmm/channelizer/example_design/top.qsys"
   displayName="top"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="tristate_conduit"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="tristate_conduit"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IConnectionKit"
   subtype=""
   factory="BeanElementFactory" />
 <plugin
   name="tristate_conduit"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Tristate Conduit Connection"
   version="25.1"
   description=""
   tags=""
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IConnection"
   factory="BeanElementFactory" />
 <plugin
   name="tristate_conduit_master"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Tristate Conduit Master"
   version="25.1"
   description="Tri-state conduit masters are used by on-chip controllers to drive off-chip components"
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <plugin
   name="tristate_conduit_slave"
   file="dsp/lib/helpers/com.altera.sopcmodel.jar"
   displayName="Tristate Conduit Slave"
   version="25.1"
   description="Tri-state conduit slaves grant access to off-chip components"
   tags="AUTHORSHIP=Altera Corporation"
   categories=""
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.entityinterfaces.IMutableConnectionPoint"
   factory="BeanElementFactory" />
 <component
   name="tse_1588"
   file="ethernet/altera_eth_tse_design_example/tse_ieee1588/tse_1588.qsys"
   displayName="tse_1588"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="tse_1588"
   file="ethernet/altera_eth_tse_design_example/tse_ieee1588_a10/tse_1588.qsys"
   displayName="tse_1588"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="up_avalon_irda_driver"
   file="university_program/communication/altera_up_avalon_irda/altera_up_avalon_irda_sw.tcl"
   displayName="up_avalon_irda_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_irda"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="up_avalon_ps2_driver"
   file="university_program/input_output/altera_up_avalon_ps2/altera_up_avalon_ps2_sw.tcl"
   displayName="up_avalon_ps2_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_ps2"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="up_avalon_rs232_driver"
   file="university_program/communication/altera_up_avalon_rs232/altera_up_avalon_rs232_sw.tcl"
   displayName="up_avalon_rs232_driver"
   version="17.1"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_rs232"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <plugin
   name="up_avalon_usb_driver"
   file="university_program/input_output/altera_up_avalon_usb/altera_up_avalon_usb_sw.tcl"
   displayName="up_avalon_usb_driver"
   version="18.0"
   description=""
   tags="SW_DRIVER_OS_TYPE=hal /// SW_DRIVER_ASSOCIATED_HW_MODULE=altera_up_avalon_usb"
   categories="driver_element"
   type="com.altera.entityinterfaces.IElementClass"
   subtype="com.altera.embeddedsw.bsp.elements.IBaseSoftwareElement"
   factory="EmbeddedSwTclDriverFactory" />
 <component
   name="usb"
   file="hps/hard_peripheral_logical_view/usb/usb_hw.tcl"
   displayName="Synopsys USB"
   version="25.1"
   description=""
   tags="CONNECTION_TYPES=axi,clock,interrupt,reset /// INTERNAL_COMPONENT=true"
   categories=""
   factory="TclModuleFactory">
  <tag2 key="ALLOW_GREYBOX_GENERATION" value="false" />
  <tag2 key="ANALYZE_HDL" value="auto" />
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="ELABORATION_CALLBACK" value="elaborate" />
  <tag2 key="INSTANTIATE_IN_SYSTEM_MODULE" value="true" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="true" />
  <tag2 key="TCL_PACKAGE_VERSION" value="12.0" />
 </component>
 <component
   name="vfb_writer_reader"
   file="vip/ip_library/full_ip/alt_vip_cl_vfb/vfb_writer_reader_hw.tcl"
   displayName="Video Writer Reader"
   version="25.1"
   description="Test component for the Frame Buffer."
   tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
   categories="DSP/Video and Image Processing"
   factory="TclModuleFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_QSYS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_QUARTUS" value="true" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
  <tag2 key="COMPOSITION_CALLBACK" value="vfbrw_composition_cb" />
  <tag2 key="OPAQUE_ADDRESS_MAP" value="false" />
  <tag2
     key="SUPPORTED_DEVICE_FAMILIES"
     value="Cyclone IV E /// Cyclone IV GX /// Cyclone V /// Cyclone 10 LP /// Arria II GX /// Arria II GZ /// Arria V /// Arria V GZ /// Arria 10 /// MAX 10 /// Stratix IV /// Stratix V" />
  <tag2 key="TCL_PACKAGE_VERSION" value="16.1" />
  <documentUrl
     displayName="User Guide"
     type="OTHER"
     url="https://documentation.altera.com/#/link/bhc1411020596507/bhc1411019828278" />
  <documentUrl
     displayName="Release Notes"
     type="OTHER"
     url="https://documentation.altera.com/#/link/hco1421698042087/hco1421697985505/en-us" />
 </component>
 <component
   name="video_pll_a10"
   file="altera_dp/de_gen/arria_10/rtl/video_pll_a10.qsys"
   displayName="video_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="video_pll_a10"
   file="altera_dp/de_gen/arria_10/simulation/video_pll_a10.qsys"
   displayName="video_pll_a10"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="wrdc_mc_256b"
   file="altera_pcie/altera_pcie_hip_256_avmm/channelizer/example_design/wrdc_mc_256b.qsys"
   displayName="wrdc_mc_256b"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <component
   name="xcvr_atx_pll"
   file="altera_jesd204/ed/ed_sim/scripts/xcvr_atx_pll.qsys"
   displayName="xcvr_atx_pll"
   version="1.0"
   description=""
   tags="INTERNAL_COMPONENT=true"
   categories="System"
   factory="QsysFactory">
  <tag2 key="COMPONENT_EDITABLE" value="false" />
  <tag2 key="COMPONENT_HIDE_FROM_SOPC" value="true" />
 </component>
 <plugin
   name="xcvr_custom_gige_presets.qprs"
   file="altera_xcvr_8g_custom/xcvr_generic/xcvr_custom_gige_presets.qprs"
   displayName="xcvr_custom_gige_presets.qprs"
   version="0.0"
   description=""
   tags=""
   categories=""
   type="com.altera.sopcmodel.util.IElementPresetList"
   subtype=""
   factory="PresetFactory">
  <tag2 key="PRESET_TYPE" value="altera_xcvr_custom_phy" />
 </plugin>
</library>
