-- ******************************************************************
-- * FILENAME:  fulladd.vhd                                         *
-- * AUTHOR:    meier@msoe.edu <Dr. Meier>                          *
-- * DATE:      22 January 2007                                     *
-- * PROVIDES:                                                      *
-- *                                                                *
-- * - a VHDL dataflow architecture for a full add component        *
-- * - note comment style guidelines for entity ports               *
-- ******************************************************************

-- ******************************************************************
-- * ENTITY DECLARATION                                             *
-- *                                                                *
-- * A: input bit representing the column input for n-bit number A  *
-- * B: input bit representing the column input for n-bit number B  *
-- * CIN: input bit representing the carry-in to the column         *
-- * SUM: output bit representing the column sum                    *                                     *
-- * COUT: output bit representing the carry-out to the next column *
-- ******************************************************************

entity FULLADD is
port	(
			A, B, CIN: in bit;
			COUT,SUM: out bit
		);
end entity FULLADD;

-- ******************************************************************
-- * ENTITY ARCHITECTURE DESCRIPTION                                *
-- *                                                                *
-- * - dataflow description using logical and, or, xor gates        *
-- ******************************************************************

architecture DATAFLOW of FULLADD is
begin

	SUM <= (A xor B) xor CIN;
	COUT <= (A and B) or (A and CIN) or (B and CIN);

end architecture DATAFLOW;