-- *************************************************************
-- * FILENAME:  hex7seg.vhd                                    *
-- * AUTHOR:    meier@msoe.edu                                 *
-- * DATE:      26 January 2007                                *
-- * PROVIDES:  a VHDL with-select implemenation of a hex7seg  *
-- *            decoder for active low LEDs (0-9,A-F)          *
-- *                                                           *
-- *            hex7seg decoders are the component that is     *
-- *            responsible for decoding the binary input      *
-- *            number into the ON/OFF patterns for the 7-seg  *
-- *            display                                        *
-- *                                                           *
-- *            active-low assertion means the LEDs turn on    *
-- *            with 0 on the LED signal and off with 1 (5V)   *
-- *                                                           *
-- * HOW-TO USE:                                               *
-- * - use this component in other entities to convert the     *
-- *   binary input nibble to the ON/OFF signals for the LEDs  *
-- *                                                           *
-- * STYLE GUIDE COMMENT                                       *
-- * - top-level entities should describe how to use the lab   *
-- *   solution (i.e. the switches connected to, etc) if the   *
-- *   top-level entity is implemented in a lab chip           *
-- * - top level entities must specify their pins and devices  *
-- *   if implemented in a lab chip -- do this in the entity   *
-- *   comments as shown below                                 *
-- *                                                           *
-- *************************************************************

-- *************************************************************
-- * ENTITY DECLARATION                                        *
-- * - I3, I2, I1, I0: the hex input                           *
-- * - A,B,C,D,E,F,G : the segment outputs                     *
-- *************************************************************
-- * PIN ASSIGNMENTS                                           *
-- * - none because this is not a top-level component          *
-- *                                                           *
-- * STYLE GUIDE COMMENT                                       *
-- * - if this was a top-level entity then this comment section*
-- *   would state the chip used (Example:  Altera EPF10KRC240)*
-- *   and provide a list of pin assignments                   *
-- * - it would look something like this:                      *
-- *                                                           *
-- *   Device: Altera EPF10KRC240                              *
-- *   I3: pin 12                                              *
-- *   I2: pin 11                                              *
-- *   I1: pin 10                                              *
-- *   etc.                                                    *
-- *                                                           *
-- * Why put it here rather than in the file comment block?    *
-- * - because the entity declaration declares "pins" into the *
-- *   entity so it makes sense to let the reader know what    *
-- *   pins of the chip implementing the circuit are attached  *
-- *   here in this section                                    *
-- *************************************************************

entity HEX7SEG is
port
	(
		I3,I2,I1,I0 : in bit;
		A,B,C,D,E,F,G: out bit
	);
end entity HEX7SEG;

-- *************************************************************
-- * ARCHITECTURE DESCRIPTION                                  *
-- * - with-select dataflow architecture for each output       *
-- *                                                           *
-- * A minterms(1,4,11,13)                                     *
-- * B minterms(5,6,11,12,14,15)                               *
-- * C minterms(2,12,14,15)                                    *
-- * D minterms(1,4,7,9,10,15)                                 *
-- * E minterms(1,3,4,5,7,9)                                   *
-- * F minterms(1,2,3,7,13)                                    *
-- * G minterms(0,1,7,10,12)                                   *
-- *                                                           *
-- * STYLE GUIDE COMMENT                                       *
-- * - components used should be included in the comments of   *
-- *   structural architectures                                *
-- * - it would look something like this:                      *
-- *   - component FULLADD:  a full adder                      *
-- *   - component COMPARE4: a 4-bit comparator                *
-- *************************************************************

architecture DATAFLOW of HEX7SEG is
begin

	with I3&I2&I1&I0 select
		A <= '1' when B"0001",
		     '1' when B"0100",
		     '1' when B"1011",
		     '1' when B"1101",
		     '0' when others;
	

	-- this file deliberately left incomplete

end architecture DATAFLOW;