-- ****************************************************************
-- * FILENAME:  prime.vhd                                         *
-- * AUTHOR:    meier@msoe.edu <Dr. M.>                           *
-- * DATE:      10 Dec 2006                                       *
-- * PROVIDES:                                                    *
-- *                                                              *
-- * - a 4-bit prime number detector using logic statements       *
-- * - shorthand notation: F(ABCD) = SUMm(1,2,3,5,7,11,13)        *
-- * - canonical:F=A'B'C'D+A'B'CD'+A'B'CD+A'BC'D+A'BCD+AB'CD+ABC'D*
-- * - minimized:F=A'D+BC'D+B'CD+A'B'C                            *
-- *                                                              *
-- * VHDL STYLE GUIDE                                             *
-- * - comments begin with -- symbols and are line comments       *
-- * - the language is case insensitive (IS and is are equal)     *
-- * - MOST people use lowercase letters for keywords and         *
-- *   UPPERCASE letters for pin, signal, entity, and component   *
-- *   names. This style allows user NAMED items to pop off the   *
-- *   page and stand out while keywords blend back into the page.*
-- * - SOME people use the opposite strategy and write keywords in*
-- *   uppercase and names in lowercase.  The CE1900 textbook does*
-- *   this style. Either style is correct.  Mixing Uppercase and *
-- *   Lowercase is not as commonly used by VHDL programmers.  Of *
-- *   course this Mixed Case strategy is Very Common in languages*
-- *   like C/C++ or Java.                                        *
-- * - MANY VHDL programmers use banner comments like this one    *
-- *   to separate the regions of their VHDL code.  It visually   *
-- *   helps to quickly find areas of interest.                   *
-- * - Indentation with one tab is used to delimit statement parts*
-- *                                                              *
-- * STEPS FOR A QUARTUS PROJECT                                  *
-- *                                                              *
-- * 1.  Start Quartus                                            *
-- * 2.  File:New Project Wizard:Complete Dialog Box:Name=prime   *
-- *     Review CE1900 schematic tutorial for project creation    *
-- * 3.  File:New:VHDL File                                       *
-- * 4.  Enter the VHDL file in the text editor                   *
-- * 5.  File:Save:Accept filename "prime"                        *
-- * 6.  Processing:Start Compilation                             *
-- * 7.  Simulate using the same steps as for schematic projects  *
-- *     Review CE1900 schematic tutorial for simulation steps    *
-- * 8.  Examine the schematic created from the VHDL by using     *
-- *     Tools:Netlist Viewers:RTL Viewer                         *
-- ****************************************************************

-- ****************************************************************
-- * ENTITY PIN DECLARATIONS                                      *
-- *                                                              *
-- * - entities are functional blocks in a system block diagram   *
-- * - entity files have two parts: pin declaration and blueprint *
-- * - pin declarations start the entity description file         *
-- * - the syntax is very sentence-like with lots of keywords     *
-- * - port is a keyword meaning "exit or entry point" - a pin!   *
-- * - each pin is listed with direction and type                 *
-- * - inputs are "in" direction, outputs are "out" direction     *
-- * - the type of basic digital signals is "bit" (binary digit)  *
-- *   a binary signal carrying 0 (0V) or 1 (5V : standard ICs)   *
-- ****************************************************************

entity PRIME is
port(
		A : in bit;
		B : in bit;
		C : in bit;
        D : in bit;
		PRIME : out bit
	);
end entity PRIME;

-- ****************************************************************
-- * ENTITY BLUEPRINT : ARCHITECTURE DESCRIPTION                  *
-- * - definition of architecture: the complex or carefully       *
-- *   designed structure of something -Oxford American Dictionary*
-- * - the architecture blueprint describes the entity's behavior *
-- * - the syntax is very sentence-like with lots of keywords     *
-- * - architecture names have some standards that people follow  *
-- *                                                              *
-- *   1.  A DATAFLOW architecture uses logic statements to       *
-- *       describe signal voltages that don't exhibit memory-like*
-- *       behavior.  CE1900 circuits DO NOT exhibit memory-like  *
-- *       behavior and thus a DATAFLOW style of description is   *
-- *       common in CE1900 VHDL descriptions.                    *
-- *   2.  A STRUCTURAL architecture uses wiring statements to    *
-- *       interconnect entities at the block diagram level.      *
-- *       CE1900 will use this type of architecture occasionally.*
-- *   3.  A BEHAVIORAL architecture describes circuits with      *
-- *       memory-like behavior.  CE1910 discusses circuits with  *
-- *       memory-like behavior.  Thus, this type of architecture *
-- *       will be common in CE1910 but NOT in CE1900.  CE1900    *
-- *       students SHOULD NOT name their architectures with the  *
-- *       "behavioral" name.                                     *
-- *                                                              *
-- * - This DATAFLOW architecture will blueprint the entity       *
-- *   behavior using a logical assignment statement for the      *
-- *   K-map minimized equation.                                  *
-- *                                                              *
-- * - VHDL keywords to study in this example program:  entity,   *
-- *   is, port, in, out, end, architecture, of, begin, assign    *
-- *   arrow (<=),and,or,not                                      *
-- ****************************************************************

architecture DATAFLOW of PRIME is
begin

	PRIME <= (not A and D) or 
	     	 (B and not C and D) or 
	         (not B and C and D) or
	         (not A and not B and C);
		 
end architecture DATAFLOW;