-- ****************************************************************
-- * FILENAME:  prime.vhd                                         *
-- * AUTHOR:    meier@msoe.edu <Dr. M.>                           *
-- * DATE:      10 Dec 2006                                       *
-- * PROVIDES:                                                    *
-- *                                                              *
-- * - a 4-bit prime number detector using logic statements       *
-- * - shorthand notation: F(ABCD) = SUMm(1,2,3,5,7,11,13)        *
-- * - canonical:F=A'B'C'D+A'B'CD'+A'B'CD+A'BC'D+A'BCD+AB'CD+ABC'D*
-- * - minimized:F=A'D+BC'D+B'CD+A'B'C                            *
-- *                                                              *
-- * NEW THINGS TO EXPLORE IN THIS EXAMPLE                        *
-- * - You can see the equations for a function as minimized by   *
-- *   the Quartus software after compilation.  To do this:       *
-- *   Tools:Options:General:Processing:Select Automatically      *
-- *   generate equation files during compilation.                *
-- * - To see the Quartus compiled equations complete a compile   *
-- *   of your VHDL.  Then, in the compilation report workspace   *
-- *   tab (it will be opened automatically during compile) you   *
-- *   choose the "Fitter" report and "equations" sub-report.     *
-- * - To understand the equations:  Quartus uses & for and, # for*
-- *   or, ! for not, and $ for xor.  Note that the Quartus       *
-- *   minimized equations MIGHT NOT match your K-map minimized   *
-- *   equations because Quartus may have taken the algebra one   *
-- *   or more steps farther than simply using the combining      *
-- *   theorem in a K-map.  Sometimes the Quartus equations will  *
-- *   match the K-map minimized equations you derive.  In all    *
-- *   cases, if your described the circuit correctly then your   *
-- *   equations and the Quartus equations are identical circuits *
-- *   in different algebraic forms.                              *
-- ****************************************************************

-- ****************************************************************
-- * ENTITY PIN DECLARATIONS                                      *
-- ****************************************************************

entity PRIME is
port(
		A : in bit;
		B : in bit;
		C : in bit;
        D : in bit;
		PRIME : out bit
	);
end entity PRIME;

-- ****************************************************************
-- * ENTITY BLUEPRINT : ARCHITECTURE DESCRIPTION                  *
-- *                                                              *
-- * - This DATAFLOW architecture will blueprint the entity       *
-- *   behavior using a logical assignment statement for the      *
-- *   canonical equations.  Read the banner comment at the start *
-- *   of this file and compare the final Quartus equations to    *
-- *   the K-map minimized equation.                              *
-- *                                                              *
-- * VHDL KEYWORDS TO STUDY IN THIS EXAMPLE                       *
-- * - there are no new keywords presented in this example        *
-- ****************************************************************

architecture DATAFLOW of PRIME is
begin

	PRIME <= (not A and not B and not C and D) or
	         (not A and not B and C and not D) or
	         (not A and not B and C and D)     or
	         (not A and B and not C and D)     or
	         (not A and B and C and D)         or
	         (A and not B and C and D)         or
	         (A and B and not C and D);
		 
end architecture DATAFLOW;