-- ******************************************************************
-- * FILENAME:	rca4.vhd                                            *
-- * AUTHOR:    meier@msoe.edu <Dr. Meier>                          *
-- * DATE:      22 January 2007                                     *
-- * PROVIDES:                                                      *
-- *                                                                *
-- * - a VHDL structural architecture of a 4-bit ripply carry adder *
-- * - port maps 4 full add components to input pins, output pins,  *
-- *   and internal signals                                         *
-- * - uses the MSOE standard signal naming scheme:  SIG_NAME       *
-- *   where NAME represents the meaning of the signal              *
-- *                                                                *
-- ******************************************************************

-- ******************************************************************
-- * ENTITY DECLARATION                                             *
-- *                                                                *
-- * A : a 4-bit input bus representing number A                    *
-- * B : a 4-bit input representing number B                        *
-- * C0: the carry-in bit for column 0                              *
-- * SUM: a 4-bit output bus representing the result of A + B       *
-- * C4: the carry-out bit from the addition                        *
-- ******************************************************************
-- * EXPLANATION                                                    *
-- *                                                                *
-- * - structural architectures interconnect components with wires  *
-- * - components are other VHDL or schematic designs               *
-- * - components are declared INSIDE the architecture since they   *
-- *   are INSIDE this entity                                       *
-- * - REMEMBER:  the entity declaration only declares ports: in    *
-- *   and out pins of the functional block                         *
-- * - REMEMBER:  the architecture declares internal components and *
-- *   internal signal wires                                        *
-- * - REMEMBER:  internal signal wires interconnect components and *
-- *   are NOT connected directly to inputs and outputs             *
-- ******************************************************************
-- * PROJECT MANAGEMENT COMMENTS                                    *
-- *                                                                *
-- * - each component can be designed as a separate project in its  *
-- *   own directory so that it can be simulated separately         *
-- * - higher level entities can "include" the VHDL or schematic    *
-- *   file of a lower-level component during project creation by   *
-- *   adding the file to the project through the Project menu or   *
-- *   the project wizard dialog boxes                              *
-- * - higher level entities can also "include" the lower level     *
-- *   entity by copying the files to the higher level project      *
-- *   directory -- this seems like too much work, see bullet above *
-- * - in any project, Quartus must know where to find all component*
-- *   design diagrams:  add the files to the project or copy to the*
-- *   project directory                                            *
-- ******************************************************************

entity RCA4 is 
port(
		-- bit_vectors are collections/sets of wires/pins
		-- they carry the same name 
		-- the total number is declared with (k downto 0)
		-- they are indexed in the architecture with [n] notation
			
		A, B: in bit_vector(3 downto 0); 
		C0: in bit;
		C4: out bit;
		SUM: out bit_vector(3 downto 0)
	);
end entity RCA4;

-- ******************************************************************
-- * ENTITY ARCHITECTURE DESCRIPTION                                *
-- *                                                                *
-- * - internal signals are declared                                *
-- * - components are declared                                      *
-- * - components are port mapped, wires of this entity are wired to*
-- *   the pins of the component                                    *
-- ******************************************************************

architecture STRUCTURAL of RCA4 is

	-- internal signals are declared
	-- signals do not carry direction in or out (they are not pins)
	
	signal	SIG_C1,SIG_C2,SIG_C3 : bit;	
	
	-- internal components are declared
	-- copy the entity declaration, paste it in here, change entity to component
	
	component FULLADD is
	port(
			A, B, CIN: in bit;
			COUT,SUM: out bit
		);
	end component FULLADD;
	
begin

	-- port map each internal component to inputs, outputs, signals
	-- components are typically named "U" on circuit boards
	-- many VHDL designers follow the U convention in structural archs
	
	-- format is NAME: COMPONENT port map(connections)
	-- this example illustrates positional mapping
	-- each of the components connections as declared in the component
	--  statement is mapped to a signal/pin in THIS entity
	
	U0: FULLADD port map(A(0),B(0),C0,SIG_C1,SUM(0));
	U1: FULLADD port map(A(1),B(1),SIG_C1,SIG_C2,SUM(1));
	U2: FULLADD port map(A(2),B(2),SIG_C2,SIG_C3,SUM(2));
	U3: FULLADD port map(A(3),B(3),SIG_C3,C4,SUM(3));
	
end architecture STRUCTURAL;