-- ******************************************************************
-- * FILENAME:	rca8.vhd                                            *
-- * AUTHOR:	meier@msoe.edu <Dr. Meier>                          *
-- * DATE:      22 January 2007                                     *
-- * PROVIDES:                                                      *
-- *                                                                *
-- * - a structural VHDL implementation of an 8-bit ripple-carry    *
-- *   adder component                                              *
-- * - this example illustrates the use of internal signal busses   *
-- * - this example illustrates the use of components               *
-- * - this example illustrates the use of port maps                *
-- * - STUDY the RCA4 tutorial file before attempting this tutorial *
-- ******************************************************************
-- * QUARTUS PROJECT MANAGEMENT                                     *      
-- *                                                                *
-- * - make a new project for RCA8                                  *
-- * - add the fulladd.vhd file using the Add Files option in the   *
-- *   proejct menu                                                 *
-- ******************************************************************

-- ******************************************************************
-- * ENTITY DECLARATION                                             *
-- *                                                                *
-- * - Entity declarations should ALWAYS include a comment block    *
-- *   like this that lists the inputs and outputs                  *
-- * - Include this comment block EVEN IF your instructor hasn't    *
-- *   enforced it.  This is the MSOE computer engineering standard *
-- * - Include pin numbers with each port if you have assigned them *
-- *   to the pins of a laboratory board and you are submitting     *
-- *   the solution to the instructor.                              *
-- * - See the fulladd and rca4 tutorial files for good examples    *
-- *                                                                *
-- * - A: an 8-bit input bus representing the input number A        *
-- * - B: an 8-bit input bus representing the input number B        *
-- * - C0: the input carry to column 0                              *
-- * - C8: the output carry from column 7                           *
-- * - SUM: an 8-bit output bus representing the result of A + B    *
-- *                                                                *
-- ******************************************************************
-- * PIN ASSIGNMENTS                                                *
-- *                                                                *
-- * - A: these signals have not been assigned to pins yet          *
-- * - B: these signals have not been assigned to pins yet          *
-- * - C0: this signal has not been assigned to pins yet            *
-- * - C8: this signal has not been assigned to pins yet            *
-- * - SUM: these signals have not been assigned to pins yet        *
-- ******************************************************************

entity RCA8 is
port(
		A, B: in bit_vector(7 downto 0);
		C0: in bit;
		C8: out bit;
		SUM: out bit_vector(7 downto 0)
	);
end entity RCA8;

-- ******************************************************************
-- * ENTITY ARCHITECTURE DESCRIPTION                                *
-- *                                                                *
-- * - structural architecture interconnecting components to pins   *
-- *   and internal signal wires                                    *
-- * - uses the MSOE computer engineering standard for signal names *
-- *   SIG_NAME where name carries meaning                          *
-- * - declares signals and components because they are INSIDE the  *
-- *   entity and thus part of the architecture                     *
-- * - after a successful compilation/elaboration use Tools:NetList *
-- *   Viewers:RTL viewer to see the circuit generated:  COOL!      *
-- ******************************************************************

architecture STRUCTURAL of RCA8 is

	-- declare internal signals
	-- using a bit_vector as a bus representing C1, C2,... C7
	
	signal SIG_C : bit_vector(7 downto 1);
	
	-- declare internal components
	-- copy the entity declaration, paste it here, change entity to component
	
	component FULLADD is
	port(
			A, B, CIN: in bit;
			COUT,SUM: out bit
		);
	end component FULLADD;
	
begin

	U0: FULLADD port map(A(0),B(0),C0,SIG_C(1),SUM(0));
	U1: FULLADD port map(A(1),B(1),SIG_C(1),SIG_C(2),SUM(1));
	U2: FULLADD port map(A(2),B(2),SIG_C(2),SIG_C(3),SUM(2));
	U3: FULLADD port map(A(3),B(3),SIG_C(3),SIG_C(4),SUM(3));
	U4: FULLADD port map(A(4),B(4),SIG_C(4),SIG_C(5),SUM(4));
	U5: FULLADD port map(A(5),B(5),SIG_C(5),SIG_C(6),SUM(5));
	U6: FULLADD port map(A(6),B(6),SIG_C(6),SIG_C(7),SUM(6));
	U7: FULLADD port map(A(7),B(7),SIG_C(7),C8,SUM(7));

end architecture STRUCTURAL;