-- ****************************************************************
-- * FILENAME:  prime.vhd                                         *
-- * AUTHOR:    meier@msoe.edu <Dr. M.>                           *
-- * DATE:      10 Sep 2015                                       *
-- * PROVIDES:                                                    *
-- *                                                              *
-- * - a 4-bit prime number detector using logic statements       *
-- * - in this example, 1 is considered prime - not correct math  *
-- * - shorthand notation: F(ABCD) = SUM(1,2,3,5,7,11,13)         *
-- * - canonical:F=A'B'C'D+A'B'CD'+A'B'CD+A'BC'D+A'BCD+AB'CD+ABC'D*
-- * - minimized:F=A'D+BC'D+B'CD+A'B'C                            *
-- *                                                              *
-- * VHDL STYLE GUIDE                                             *
-- * - comments begin with -- symbols and are line comments       *
-- * - the language is case insensitive (IS and is are equal)     *
-- * - MOST people use lowercase letters for keywords and         *
-- *   UPPERCASE letters for pin, signal, entity, and component   *
-- *   names. This style allows user NAMED items to pop off the   *
-- *   page and stand out while keywords blend back into the page.*
-- * - SOME people use the opposite strategy and write keywords in*
-- *   uppercase and names in lowercase.  The CE1901 textbook uses*
-- *   only lowercase. Any of these styles is acceptable. Mixing  *
-- *                                                              * 
-- * - MANY VHDL programmers use banner comments like this one    *
-- *   to separate the regions of their VHDL code.  It visually   *
-- *   helps to quickly find areas of interest.                   *
-- * - Indentation with one tab is used to delimit statement parts*
-- *                                                              *
-- * STEPS FOR A QUARTUS VHDL PROJECT                             *
-- *                                                              *
-- * 1.  Start Quartus                                            *
-- * 2.  File:New Project Wizard:Complete Dialog Box:Name=prime   *
-- *     Review CE1901 schematic tutorial for project creation    *
-- * 3.  File:New:VHDL File                                       *
-- * 4.  Enter the VHDL file in the text editor                   *
-- * 5.  File:Save:Accept filename "prime"                        *
-- * 6.  Processing:Start Analysis and Synthesis                  *
-- * 7.  Simulate using the same steps as for schematic projects  *
-- *     Review CE1901 schematic tutorial for simulation steps    *
-- * 8.  Examine the schematic created from the VHDL by using     *
-- *     Tools:Netlist Viewers:RTL Viewer                         *
-- ****************************************************************

-- ****************************************************************
-- * ENTITY PIN DECLARATIONS                                      *
-- *                                                              *
-- * - Entities are functional blocks in a system block diagram.  *
-- * - Entity files have two parts: pin declaration and blueprint.*
-- * - Pin declarations start the entity description file.        *
-- * - The syntax is very sentence-like with lots of keywords.    *
-- * - Port is a keyword meaning "exit or entry point" - a pin!   *
-- * - Each pin is listed with direction and type                 *
-- * - Inputs are "in" direction, outputs are "out" direction     *
-- * - The type of digital signals is "std_logic", defined in     *
-- *   IEEE standard 1164. Include the IEEE library in each file. *
-- ****************************************************************

-- include IEEE signal library 
library ieee;
use ieee.std_logic_1164.all;

-- entity declaration
entity PRIME is
port(A : in std_logic; 
     B : in std_logic;
     C : in std_logic;
     D : in std_logic;
     PRIME : out std_logic);
end entity PRIME;

-- ****************************************************************
-- * ENTITY BLUEPRINT : ARCHITECTURE DESCRIPTION                  *
-- * - Definition of architecture: the complex or carefully       *
-- *   designed structure of something (Oxford American Dict.)    *
-- * - The architecture blueprint describes the entity's behavior.*
-- * - The syntax is very sentence-like with lots of keywords.    *
-- * - Architecture names have some standards that people follow. *
-- *                                                              *
-- *   1.  A DATAFLOW architecture uses logic statements to       *
-- *       describe signal voltages that don't exhibit memory-like*
-- *       behavior.  CE1901 circuits DO NOT exhibit memory-like  *
-- *       behavior and thus a DATAFLOW style of description is   *
-- *       common in CE1901 VHDL descriptions.                    *
-- *   2.  A STRUCTURAL architecture uses wiring statements to    *
-- *       interconnect entities at the block diagram level.      *
-- *       CE1901 will use this type of architecture often.       *
-- *   3.  A BEHAVIORAL architecture describes circuits with      *
-- *       memory-like behavior.  CE1911 discusses circuits with  *
-- *       memory-like behavior.  Thus, this type of architecture *
-- *       will be common in CE1911 but NOT in CE1901.  CE1901    *
-- *       students SHOULD NOT name their architectures with the  *
-- *       "behavioral" name.                                     *
-- *                                                              *
-- * - This DATAFLOW architecture will blueprint the entity       *
-- *   behavior using a logical assignment statement for the      *
-- *   K-map minimized equation.                                  *
-- *                                                              *
-- * - VHDL keywords to study in this example program:  entity,   *
-- *   is, port, in, out, end, architecture, of, begin, assign    *
-- *   arrow (<=),and,or,not                                      *
-- ****************************************************************

architecture DATAFLOW of PRIME is
begin

	PRIME <= (not A and D) or 
	     	 (B and not C and D) or 
	         (not B and C and D) or
	         (not A and not B and C);
		 
end architecture DATAFLOW;