Day 1

• Draw the buffer gate symbol.
• Write the truth table for the buffer gate.
• Write the Boolean equation for the buffer gate.
• Draw the NOT gate.
• Write the truth table for the NOT gate.
• Write the Boolean equation for the NOT gate.
• Draw the logic gate symbols for the 2-input AND, OR, NAND, NOR, XOR, and XNOR gates.
• Write the truth tables for the 2-input AND, OR, NAND, NOR, XOR, and XNOR gates.
• Write the Boolean equations for the 2-input AND, OR, NAND, NOR, XOR, and XNOR gates.
• Extend the AND, OR, XOR, and XNOR gates to n-inputs.

Day 2

• Define the power supply voltages GND and VDD.
• Contrast the value of VDD common in the 1970s and 1980s technologies with the value of VDD common in today's circuits.
• Define the driver and receiver in a gate-level interconnection.
• Justify assigning numerical values 0 and 1 to real voltages VOL and VOH.
• Define noise margin.
• Draw the classic noise margin graph. Identify VOH, VOL, VIL, and VIH on the diagram.
• Write the noise margin equations NML and NMH.
• Draw the ideal voltage-transfer characteristic (VTC).
• Explain how the ideal VTC switching threshold of VDD/2 affects noise margins.
• Draw a real VTC curve.
• Explain how real VTC unity gain points affect the noise margins.
• State the VOH value for 5V TTL.
• State the VOH value for 5V CMOS.
• Describe the interfacing compatability of the four possibilities of TTL and CMOS interconnection (TTL/TTL, CMOS/CMOS, TTL/CMOS, CMOS/TTL).

Day 3

• Draw the levels-of-design pyramid showing system level at the top, gate level in the middle, and transistor level at the bottom.
• Describe how encapsulation of components into hierarchical levels makes design diagrams smaller as you move up the levels-of-design pyramid.
• Draw the three-terminal NMOS and PMOS transistor symbols.
• Describe the gate on-off characteristics of NMOS and PMOS transistors.
• Describe the purpose of the pull-up network in a CMOS transistor circuit design.
• Describe the purpose of the pull-down network in a CMOS transistor circuit design.
• State the general rules-of-thumb for CMOS transistor organization in the pull-up and pull-down networks.
• Draw the CMOS schematic for a NOT gate.
• Draw the CMOS schematic for an n-input NAND gate.
• Draw the CMOS schematic for an n-input NOR gate.
• Extend the CMOS NAND and NOR schematics to become AND and OR gates.