Day 1

• Use three variable K-maps to design minimized digital logic circuits.
• Use four variable K-maps to design minimized digital logic circuits.
• Calculate the reduction ratio (minimized gates / canonical gates) for a minimized circuit.
• Use Quartus to design, simulate, compare and contrast canonical and minimized circuits.

Day 2

• Use K-maps to implement functions with don't care conditions.
• Compare and contrast the circuits that result from different don't care choices for the same problem.
• Reverse-engineer a K-map and truth table from a given logic circuit.
• Use Quartus to design and simulate circuits with don't care conditions.

Day 3

• Use bubble pushing to convert K-map minimized sum-of-products logic circuits to NAND-NAND circuits.
• Use Quartus to design and simulate minimized circuits and NAND-NAND circuits.

Instructor Led Laboratory Examples

• Implement canonical equations in Quartus using a VHDL gate-level architecture with keywords not, and, or, nand, nor, xor, xnor, etc.