Day 1

• Write the truth table for a 2:1 multiplexer.
• Derive the K-map minimized equation for a 2:1 multiplexer.
• Draw the gate-level circuit for a 2:1 multiplexer.
• Build 4:1, 8:1, and 16:1 multiplexers using 2:1 multiplexers.
• Implement canonical equations using n:1 multiplexers.
• Use Quartus to design and simulate multiplexer circuits.

Day 2

• Use words to describe the behavior of a decoder.
• Describe the one-hot condition of decoder outputs.
• Write the truth table for a 2:4 decoder.
• Derive the canonical equations for the 2:4 decoder output.
• Use Boolean algrebra and K-maps to determine if the 2:4 decoder output equations can be reduced.
• Draw the final circuit of a 2:4 decoder.
• Draw the standard logic symbol for a 2:4 decoder.
• Extend the techniques used to design a 2:4 decoder to a 3:8 decoder.
• Use Quartus to design and simulate decoder circuits.

Day 3

• Use words to describe the behavior of a encoder.
• Describe the difference between a standard encoder and a priority encoder.
• State why priority encoders are preferred components. In other words, what disadvantage of standard encoders is removed by the priority encoder.
• Write the truth table for a 4:2 priority encoder.
• Derive the canonical equations for the 4:2 priority encoder.
• Use Boolean algrebra and K-maps to determine if the 4:2 priority encoder output equations can be reduced.
• Draw the final circuit of a 4:2 priority encoder.
• Draw the standard logic symbol for a 4:2 priority encoder.
• Extend the techniques used to design a 4:2 priority encoder to an 8:3 priority encoder.
• Use Quartus to design and simulate encoder circuits.

Instructor Led Laboratory Examples

• Implement canonical equations as multiplexers in Quartus using a VHDL with-select architecture.
• Simulate the VHDL circuit using the Quartus waveform editor.