WEEK 6 LEARNING OBJECTIVES

Day 1

• Compare and contrast ideal and real gates.
• State why real gates have delay.
• List the power-of-10 units used for timing electric circuits. These units represent speeds faster than one second!
• Define the gate propagation delay.
• Illustrate propagation delays on a timing diagram.
• Describe how the critical path affects circuit propagation delay.
• Calculate the propagation delay for example circuits.

Day 2

• Define glitch.
• Describe why combinational glitches occur.
• Illustrate glitches on timing diagrams.
• State how glitches can be identified in K-maps.
• Eliminate glitches using a consensus term.
• State why glitches cannot be completely removed in most circuits.

Day 3

• This day is reserved for review and extra practice of course material.