Day 1

• Review binary addition and subtraction.
• Define bitslice.
• Identify the inputs and outputs of a circuit that adds two numbers.
• State how the inputs and outputs of the least significant adder column differs from the inputs and outputs of every other column in the adder.
• Use a K-map to design the half-adder circuit.
• Use a K-map to design the full-adder circuit.
• Use the full adder component to design an n-bit ripple-carry adder.
• Derive the equation for ripply-carry adder delay.
• Extend the ripple-carry adder to a ripple-carry add-subtract component that uses XOR gates and a control signal called SUB to create the twos-complement of B.

Day 2

• Describe how carry-lookahead adders improve performance.
• Describe the role of the carry and generate signals in the carry-lookahead adder.
• Write the generate equation for the i-th bit of an n-bit carry-lookahead adder.
• Write the propagate equation for the i-th bit of an n-bit carry-lookahead adder.
• Write the carry equation for the i-th bit of an n-bit carry-lookahead adder.
• Use recursion to derive the equations for the 4-bit carry-lookahead adder.
• Derive the equation for the carry-lookahead adder delay.

Day 3

• Review carry look-ahead adders and the carry look-ahead circuit.
• Describe how carry-select adders improve performance.
• Draw the carry-select adder in 8-bits and 16-bits.
• Compare the performance and gate-usage of ripple-carry, carry look-ahead, and carry-select adders.

Instructor Led Laboratory Examples

• Implement a ripple-carry adder as a VHDL structural architecture.
• Simulate the VHDL circuit using the Quartus waveform editor.