Note: The first week of CE1911 uses the laboratory period as a fourth lecture period.

Day 1

• Compare and contrast combinational and sequential systems.
• Define the "state" of a memory element.
• Compare and contrast level-sensitive and edge-triggered behavior.
• Describe the role of a clock signal.
• Identify the rising-edge and falling-edge of a clock.
• Define the duty-cycle of a periodic clock signal.
• Define bistable element.
• Draw the basic 1-bit memory as cross-coupled inverters.
• Describe how the 1-bit cross-coupled inverter memory functions.

Day 2

• Add storage control to the 1-bit memory by replacing the cross-coupled inverters with cross-coupled NOR gates.
• Write the SR-latch truth table.
• Draw the SR-latch logic symbol.
• Describe the SR-latch memory behavior.
• State the SR-latch fundamental control flaw.
• Write the D-latch truth table.
• Draw the D-latch logic symbol.
• Describe the D-latch memory behavior.
• State how the D-latch removes the fundamental control flaw.

Day 3

• Write the truth table of the DFF.
• Draw the logic symbol for the DFF.
• Draw the master-slave DFF internal circuit.
• Describe the DFF memory behavior.
• Draw the logic symbol for the n-bit register.
• Draw the internal circuit of an n-bit register.
• Draw timing diagrams that illustrate DFF and register behavior.

Day 4

• Write the truth table of a DFF with enable control.
• Draw the logic symbol for a DFF with enable control.
• Draw the internal circuit for a DFF with enable control.
• Write the truth table of a DFF with synchronous reset control.
• Draw the logic symbol for a DFF with synchronous reset control.
• Draw the internal circuit for a DFF with synchronous reset control.
• Write the truth table of a DFF with asynchronous reset control.
• Draw the logic symbol for a DFF with asynchronous reset control.
• Draw the internal circuit for a DFF with asynchronous reset control.
• Draw timing diagrams that illustrate reset and enable control signals.
• Draw the logic symbol for an n-bit register with enable (load) and asynchronous reset (rst) control signals.