WEEK 6 LEARNING OBJECTIVES

Day 1

• Compare and contrast ideal and real flip-flops.
• State why changing inputs could cause incorrect flip-flop behaviors during clock-edge sampling.
• Define the flip-flop setup time.
• Define the flip-flop hold time.
• Illustrate the flip-flop setup and hold times on a timing diagram.
• Describe the dynamic discipline.
• Examine 7400 family datasheets and identify setup and hold times for various family members.
• Describe the dynamic discipline.
• Define aperture time.
• Define the clock-to-Q contamination delay.
• Define the clock-to-Q propagation delay.
• Illustrate aperture, contamination, and propagation delay on a timing diagram.

Day 2

• Write the equation for minimum clock period, Tc.
• Write the equation for maximum propagation delay, tpd.
• Define the sequencing overhead.
• Define the setup time constraint.
• Write the equation for minimum propagation delay, tcd.
• Define the hold time constraint.
• State why hold time constaints are costly.
• Work example problems given flip-flop and logic gate specifications.

Day 3

• Define clock skew.
• List factors that contribute to clock skew.
• Describe how clock skew affects the minimum clock period and the maximum propagation delay.
• Work example problems given clock skew, flip-flop and logic gate specifications.