-- ********************************************************
-- * project:     control
-- * filename:    control.vhd
-- * author:      << insert your name here >>
-- * date:        MSOE Spring Quarter 2020
-- * provides:    a control circuit for the ARMv4 ISA
-- *              instructions implemented in the CE1921
-- *              single-cycle processor
-- * approach:    use when-else statements 
-- ********************************************************

-- use library packages 
-- std_logic_1164: 9-valued logic signal voltages 
library ieee;
use ieee.std_logic_1164.all;

-- functional block symbol
-- inputs
--    IBUS is the upper 12-bits of the 32-bit machine code
--    Z is the zero condition code flag from the CPSR
-- outputs 
--    PCSRC:   0 = BranchAddress    1 = PC+4
--    A2SRC:   0 = Rm               1 = Rd 
--    REGWR:   0 = Regfile Write    1 = Regfile does not write 
--    ALUSRCB: 0 = imm32            1 = RD2 from Regfile 
--    ALUS:    0 = ADD              1 = SUb
--             2 = AND              3 = OR
--             4 = XOR              5 = A
--             6 = B                7 = 0X00000001
--    CSPRWR:  0 = CPSR Write       1 = CPSR does not write 
--    MEMWR:   0 = Data Mem Write   1 = Data Mem does not write
--    REGSRC:  0 = Data Mem Value   1 = ALU Value

entity CONTROL is 
port(IBUS:     in  std_logic_vector(31 downto 20);
     Z:        in  std_logic;
     PCSRC:    out std_logic; 
     A2SRC:    out std_logic; 
     REGWR:    out std_logic; 
     ALUSRCB:  out std_logic;
     ALUS:     out std_logic_vector(2 downto 0);
     CPSRWR:   out std_logic; 
     MEMWR:    out std_logic;
     REGSRC:   out std_logic);
end entity CONTROL;

-- circuit description 
architecture DATAFLOW of CONTROL is 
   -- declare signals for the IBUS bit fields 
   -- data processing 
   signal COND : std_logic_vector(3 downto 0);
   signal OPCODE: std_logic_vector(1 downto 0);
   signal I: std_logic;
   signal CMD: std_logic_vector(3 downto 0);
   signal S: std_logic;
   -- load-store
   signal IBAR: std_logic;
   signal PUBW: std_logic_vector(3 downto 0);
   signal L: std_logic;
   -- branch 
   signal BRL: std_logic; -- the branch L bit is a different bit than Load/Store L
   
begin

   -- assign IBUS bits to internal signals 
   COND <= IBUS(31 downto 28);
   OPCODE <= IBUS(27 downto 26);
   I <= IBUS(25);
   -- << continue writing these internal signal assignments >> 
   
   
   
   
   
   -- write output equations using when-else syntax 
   -- include rows from data processing, load-store, and branch truth tables
   PCSRC <= '0' when COND=X"0" and OPCODE=B"10" and BRL='0' and Z='1' else -- beq taking branch
            -- << complete other equations taking branch >> 
            else 
           '1'; -- PC+4 for all other instructions 
            
   A2SRC <= '0' when COND=X"E" and OPCODE=B"00" and I='0' and CMD=X"4" and S='0' else -- add reg
            '0' when COND=X"E" and OPCODE=B"00" and I='1' and CMD=X"4" and S='0' else -- add imm
            -- << complete>>
            
   -- complete all equations 
   
end architecture DATAFLOW;