Day 1

• Justify the statement "Pipelined processors that execute instructions only in-order must stall on cache miss."
• Describe the process that the cache controller must complete on instruction read miss.
• Describe the process that the cache controller must complete on data read miss.
• Explain the statement "A cache is theoretically a mirror image of parts of main memory."
• Define inconsistency in terms of cache blocks.
• Describe the write-through cache consistency strategy.
• Describe the effect of write-through on the processor CPI.
• Describe the use of a write-buffer to minimize the write-through effect on process CPI.
• Describe the write-back cache coherency strategy.
• Describe how changing the width of the memory bus increases the memory bandwidth and reduces replacement time.
• Describe how synchronous DRAM and DDRAM improve the performance of the memory system.

Day 2

• Define fully-associative cache.
• State the advantages and disadvantages of fully-associative cache.
• Define set-associative cache.
• State the advantages and disadvantages of set-associative cache.
• State the mapping equation for an n-way set-associative cache.
• Diagram an n-way set-associative cache as read and write accesses occur.

Day 3

• Describe the least-recently used replacement strategy for n-way set-associative cache.
• Describe the random replacement strategy for n-way set-associative cache.
• Justify the statement "random replacement does not consider temporal locality with the same importance as least-recently used."
• Describe the use of cache levels to improve memory performance.
• Justify the statement "multiple levels of cache reduce the miss penalty at the processor."
• Draw the simple four-state cache controller finite state diagram for a direct mapped cache with write-back cache strategy.