BASIC SYSTEM PRINCIPLES

1. List the three categories of computer systems.
2. Define computer architecture.
3. List the three subcategories of computer architecture.
4. Compare and contrast the three subcategories of computer architecture: instruction set architecture, microarchitecture, and system architecture.
5. List the five classic components of a computer.
6. Define processor in the context of the five classic components of a computer.
7. Compare and contrast microprocessors and microcontrollers.
8. Define the stored-program concept.
9. Compare and contrast primary and secondary memory.
10. Draw the classic computer architecture memory hierarchy
11. List the classic memory and storage size prefixes (KB, MB, GB, etc. and how they differ in memory and storage).
12. Draw the Princeton (von Neumann) system architecture.
13. Draw the Harvard system architecture.
14. Describe the Princeton bottleneck.
15. List the advantages and disadvantages of the Princeton and Harvard system architectures.
16. Compare and contast execution time, throughput, CPU time, user CPU time, and system CPU time.
17. Calculate the average clocks per instruction (CPI) given instruction timing information.
18. Calculate CPU execution time using IC * CPI * period
19. Compare the performance of different computers by applying the performance equations to system specifications.
20. Comment on the SPEC benchmarks and their importance in performance analysis.
21. Define instruction set architecture.
22. List the four categories of instructions.
23. Describe the difference between instruction set architecture and microarchitecture.

MIPS ARCHITECTURE REVIEW

1. State the MIPS magic number.
2. State the number of MIPS registers.
3. Categorize the MIPS registers into assembly language groups.
4. Compare and contrast saved temporary and temporary registers.
5. List some core MIPS assembly language instructions.
6. Write MIPS assembly language instructions.
7. List the three MIPS instruction formats.
8. Write the MIPS R-format ALU architectural equation.
9. Write the MIPS I-format ALU architectural equation.
10. Write the MIPS I-format lw architectural equation.
11. Write the MIPS I-format sw architectural equation.
12. Write the MIPS I-format beq architectural equation.
13. Write the MIPS I-format bne architectural equation.
14. Draw the R-format instruction binary number showing the fields and associated bit positions.
15. Draw the I-format instruction binary number showing the fields and associated bit positions.
16. Draw the J-format instruction binary number showing the fields and associated bit positions.
17. Compare and contrast the single-phase and double-phase clocking strategies (using one edge versus using two edges) for calcolation and register update.
18. Describe the use of moltiplexers to select data flow in the single-cycle MIPS processor designed in lecture.

PIPELINING REVIEW

1. Describe how pipelined microarchitectures exploit instruction level parallelism to improve throughput.
2. State the number of instructions in flight every clock cycle when a basic MIPS pipelines is foll.
3. Describe how pipelining improves throughput.
4. State the theoretical pipeline speedup (compared to single-cycle) for a pipeline of length n.
5. State why the theoretical pipeline speedup cannot be achieved.
6. Use the pipeline speedup equation to calcolate real pipeline speedup based on a stall-cycle mix.
7. Describe the use of interstage registers in pipeline microarchitecture.
8. Justify the statement "Pipeline microarchitectures make very efficient time usage of components."
9. List the three types of pipeline hazards.
10. List examples of structural hazards.
11. State how structural hazards are eliminated when implementing pipelined microarchitectures.
12. Justify the Harvard organization in pipelined implementations.
13. List the two broad categories of data hazards.
14. Describe the hazard window for MIPS pipeline microarchitectures if hazard-protection is not implemented.
15. Identify load-use and register-use data hazards in code segments.
16. List the three principle techniques used to remove data hazards. Describe the advantages and disadvantages of each technique.
17. Describe how the hazard window suggests forwarding paths for data hazard prevention.
18. State the two causes of control hazards.
19. Describe the effect of unconditional and conditional branches on pipeline performance.
20. List the two principle techniques used to handle control hazards.
21. Justify advancing jump circuitry into earlier pipeline stages such as IF or ID.
22. Draw pipeline flight plans showing instructions stalling through branch decision and then flushing after a taken branch.
23. Compare and contrast the simple (predict branch not taken) and complex (statistical prediction) branch prediction techniques.
24. Describe the Lee and Smith study on branch predictors. Summarize the key result.
25. Describe how the Nair study differs from the Lee and Smith study. Summarize the key result.
26. Comment on the success of state-of-the-art branch predictors.
27. Describe the use of branch target buffers and branch history buffers as more advanced branch prediction techniques.

SUPERPIPELINING BASICS

1. Justify deepening a pipeline.
2. State the type of parallelism (spatial, temporal, or both) exploited by deepening a pipeline.
3. State how deepening a pipeline affects the pipeline speedup equation.
4. Explain how deeper pipelines are affected by hazards.
5. Explain how forwarding complexity increases in deeper pipelines.
6. List challenges faced by deeper pipelines.

MIPS R4000 SUPERPIPELINED PROCESSOR

1. Draw an organizational sketch of the MIPS R4000 processor.
2. Draw a pipeline flightplan that shows the stages of the MIPS R4000 processor using the correct stage names.
3. Describe the hazard response of the MIPS R4000 processor.

SUPERSCALAR BASICS

1. Justify extending a microarchitecture to superscalar.
2. State the type of parallelism (spatial, temporal, or both) exploited by superscalar processors.
3. Describe the challenges that superscalarism introduces that are not challenges in simple pipelines.
4. List and describe compile-time techniques, such as loop unrolling and predicated instructions, that can assist in superscalar dispatch.
5. List and describe run-time techniques, such as reservation stations and register renaming, that can assist in superscalar dispatch.
6. State how superscalarism improves on the IPC when compared to a pipelined processor.

INTEL PENTIUM PROCESSOR

1. Draw a basic organizational sketch of the Intel Pentium processor.
2. Draw a pipeline flightplan that shows the stages of the Intel Pentium processor using the correct stage names.
3. Describe the hazard response of the Intel Pentium processor.
4. List the four requirements for Intel Pentium dual-issue.
5. Describe the forwarding mechanism of the Intel Pentium processor.
6. Draw the Intel Pentium dynamic branch prediction state machine.
7. Determine the prediction made by the Intel Pentium dynamic branch prediction state machine for a given code sequence.

MOTOROLA 88110 PROCESSOR

1. Draw a basic organizational sketch of the Motorola 88110 processor.
2. Draw a pipeline flightplan that shows the stages of the Motorola 88110 processor using the correct stage names.
3. Describe the hazard response of the Motorola 88110 processor.
4. Describe the Motorola 88110 dispatch algorithm.
5. State why the Motorola 88110 includes two integer units.
6. Summarize the types of calcolations completed by each of the ten functional pipes in the Motorola 88110 microprocessor.
7. State the cycle delay for each of the ten functional pipes in the Motorola 88110 microprocessor.
8. Describe the use of the history buffer in the Motorola 88110 microprocessor. Hint: Have you searched for an 88110 paper in IEEE Explore?
9. State how the Motorola 88110 handles temporal ordering of writes to the register files.

PENTIUM PRO CASE STUDY

1. Place the Pentium Pro into historical context by describing the state of the industry and its competition.
2. Describe why the Pentium Pro was revolutionary rather than simply evolutionary.
3. Describe architectural key points for the Pentium Pro. What makes it interesting to advanced superscalar architects?
4. Sketch the basic organizational diagram for the Pentium Pro.
5. Draw the Pentium Pro flightplan diagram.
6. Describe the Pentium Pro fetch-decode process.
7. Describe the basic instruction format for a u-op.
8. Summarize the u-op translation process.
9. Translate reg-mem or mem-mem x86 instructions to example u-ops.
10. State the average number of u-ops per x86 instruction.
11. State the primary purpose of the reorder buffer.
12. Describe what gets allocated for each instruction in the reorder buffer.
13. Summarize the register renaming process implemented inside the reorder buffer.
14. State the primary purpose of the reservation station.
15. Describe the dispatch process out of the reservation station.
16. Compare and contrast the Pentium Pro main and secondary arithmetic units.
17. Describe the dual-issue limitation imposed by the Pentium Pro secondary arithmetic unit.
18. Summarize the Pentium Pro integer unit performance. Compare it to the P5 architecture.
19. List the three result types that can potentially return to the reorder buffer on each clock cycle.
20. Describe the instruction events that occur as instruction results enter the reorder buffer.
21. Summarize the Pentium Pro cache behavior.
22. State the best-case Pentium Pro instruction flight time.
23. State the average-case Pentium Pro instruction flight time.
24. Describe why the Pentium Pro has an average-case flight time rather than a fixed-case flight time.
25. Justify the use of advanced control hazard strategies on the Pentium Pro.
26. Summarize the conditional move instruction category.
27. Describe how conditional moves help eliminate specific types of control hazards.
28. Summarize example static and dynamic branch prediction strategies.
29. State the success rate of the APNT strategy for static branch prediction.
30. State the success rate of the BTFNT strategy for static branch prediction.
31. Compare and contrast the Lee and Yeh approaches to dynamic branch prediction.
32. Justify the statement "The Yeh approach tracks patterns of branches and not just a specific branch."
33. Summarize the Pentium Pro branch prediction approach and the success rate.

MULTIPROCESSING AND MULTICORE PROCESSORS

1. State reasons why drop-in cores begin emerging as a strong design theme in 21st century processors.
2. Compare and contrast symmetric and asymmetric (distributed memory) multiprocessors.
3. Describe cluster computing.
4. List the four categories in the Flynn taxonomy for multiprocessor systems.
5. Describe each of the four categories in the Flynn taxonomy for multiprocessor sytems.
6. Give examples of each of the four categories in the Flynn taxonomy for multiprocessor systems. For example, the classic PC of the 1990s is which type?
7. Sketch a basic organizational diagram for each of the four categories in the Flynn taxonomy for multiprocessor systems.
8. Describe the two subcategories of MIMD systems.
9. State the design goal set by the company consortium that developed the molticore processor case-study examined in lecture (Cell).
10. Describe the basic organizational features of the Cell multiprocessor.
11. Sketch a basic organizational diagram of the Cell multiprocessor.
12. List key architectural characteristics and strategies implemented by the Cell multiprocessor Power Processing Element (PPE).
13. List key architectural characteristics and strategies implemented by the Cell multiprocessor synergistic processor elements (SPE).
14. Describe how the Cell multiprocessor SPEs implement SIMD mathematics by varying bitwidths.
15. Describe vector processors including their history, Flynn taxonomy, and places where they have been most successful in the markeplace.
16. Describe graphics processing units (GPUs) including their history, Flynn taxonomy, and their success in today's markeplace.
17. Describe VLIW processors including their history, Flynn taxonomy, and their success rate in the marketplace.
18. Describe current trends in micro-architecture including technology greening, the return of hyperthreading, the asymptotic leveling of core count, and licensable intellectual property (IP) cores.