WEEK 5 LEARNING OBJECTIVES

Day 1

• Extend the static-CMOS inverter design to n-input NAND and NOR gates by using the series and parallel rules in the pull-up and pull-down networks.
• Design static-CMOS complex-logic circuits to meet design requirements by sizing the transistors in the pull-up and pull-down networks as multiples of the (W/L) values of the reference inverter.
• Use SPICE to verify n-input gate performance.

Day 2

• Design static-CMOS complex-logic circuits to meet design requirements by sizing the transistors in the pull-up and pull-down networks as multiples of the (W/L) values of the reference inverter.
• Use SPICE to verify design specifications.