WEEK 6 LEARNING OBJECTIVES
Day 1
- Design static-CMOS complex-logic circuits to meet
design requirements by sizing the transistors in the pull-up and
pull-down networks as multiples of the (W/L) values of the
reference inverter.
- Use SPICE to verify design specifications.
Day 2
- Design static-CMOS complex-logic circuits to meet
design requirements by sizing the transistors in the pull-up and
pull-down networks as multiples of the (W/L) values of the
reference inverter.
- UseSPICE to verify design specifications.