WEEK 6 LEARNING OBJECTIVES
Day 1
- Draw the CMOS SR latch using NOR and NAND
gate topologies.
- Analyze the CMOS SR latches to verify
correct latch behavior.
- Extend the CMOS SR latch to a latch with
enable.
- Draw the CMOS D latch.
- Analyze the CMOS D latch to verify correct
latch behavior.
- Extend the CMOS D latch to a master-slave
D flip flop (DFF) component.
Day 2
- Summarize the VLSI characteristics of DRAM,
SRAM, UV EPROM, EEPROM, FLASH, and FRAM memory components in a
table that includes volatility, cell structure, cell density,
power consumption, read speed, and write speed.
- Describe the basic DRAM cell and its
equations of operation.
- Describe the basic SRAM cell and its
equations of operation.
- Describe the basic FLASH cell and its
equations of operation.