WEEK 7 LEARNING OBJECTIVES

Day 1

• Compare and contrast static-CMOS and dynamic-CMOS.
• Convert a static-CMOS design to a dynamic-CMOS circuit.
• Design a dynamic-CMOS circuit to meet design requirements such as TPHL and TPLH.
• Characterize the power flow in dynamic-CMOS circuits.
• Simulate dynamic-CMOS circuits using SPICE to verify design specifications.
• State why dynamic-CMOS stages cannot be cascaded easily.
• Determine the maximum clock frequency for a dynamic-CMOS circuit given TPHL and TPLH data.

Day 2

• Describe the simply modification domino-logic makes to the dynamic-CMOS circuit.
• Explain how domino-logic allows cascading of dynamic-CMOS stages.
• Convert a dynamic-CMOS stage to a domino-logic stage by converting the pull-down network to the dual (ANDs become ORs, ORs become ANDs, inputs invert).