COMPUTER ARCHITECTURE

 

CS 242                                                                                   No. of hrs/week=03+03

                                                                                                                                  No. of credits =04

1. Introduction: Organization and Architecture, structure and function, why study Computer Organization & Architecture [1.1-1.3 of  Text1]                                                 1hr

2. Designing for performance, Pentium and Power PC Evolution [2.2-2.3 of Text 1]     1hr

3. Computer Components, Computer function, Interconnection structures, Bus interconnection, PCI [3.1-3.4 of Text 1]                                                                                   2hrs

4. Memory Hierarchy-Semiconductor main memory-RAM and ROM chips, memory address map, memory connection to CPU[12.1 of Text 2]                                                                 3hrs

Auxiliary Memory – Magnetic Disks, RAID, Optical memory

[12.3 of  Text 2, 6.1-6.3 of Text 1]                                                                                            2hrs

Cache Memory – Cache memory principles, elements of cache design, cache mapping techniques [12.5 of Text 2, 4.1- 4.4 of Text 1]                                                                  3hrs

Virtual Memory, memory management Hardware[12.6-12.7 of Text 2]                            2hrs

5. Instruction set Design : Machine instruction characteristic- types of operands, types of operations, Addressing modes, Instruction  formats- [Examples of Pentium and Power PC must  be emphasized] [ 10.1-10.5, 11.1-11.4 of Text 1]                                                    4hrs

6. CPU structure and Function:             processor organization, register organization, Instruction cycle, Example of Pentium and power PC processors  [12.1-12.3 of Text 1]  3hrs

7. Control Unit Operation: Micro operations, Control of the processor, hardwired Implementation, micro-programmed control [16.1-16.3,17.1-17.3 and 17.5 of  Text 1]   4hrs

8. Computer Arithmetic : The ALU, Integer arithmetic, floating point arithmetic [9.1-9.5 of Text 1, all sections must be discussed]                                                                          6hrs

9. RISC – CISC characteristics, RISC characteristics, RISC pipelining, Overlapped register windows, RISC v/s CISC, Berkeley RISC-I [13.1-13.5 & 13.8 of Text 1 and 8.8 of Text 2]                                                                                                                                           3hrs

10. Input – Output: External Devices, I-O interface, modes of transfer , ( serial, parallel Synchronous, Asynchronous) programmed I/O, [Interrupt- driven I/O, DMA, IO Channels and processors].[11.1-11.7 of Text 2, 7.1-7.6 of Text 1]                                                  6hrs

11. Parallel Processing-Pipelining , arithmetic pipeline, instruction pipeline, RISC pipeline. [9.1-9.5of Text 2]                                                                                                                        3hrs

12. Multiprocessors, Multiprocessor Organizations: Interconnection structure, interprocessor arbitration, Interprocessor communication and synchronization, Cache coherence , clusters                                                                                                                           7hrs

[18.1-18.4 of Text 1, 13.1-13.5 of Text 2]

TEXT BOOKS:

1.            Computer Organization and Architecture – William Stallings, VI edition, PHI

2.          Computer System Architecture- Morris Mano- III Edn, PHI

 

COMPUTER ARCHITECTURE(PRACTICAL)

 

The following exercises can be implemented and simulated  using VHDL/ Verilog

  1. Flip flops

a)     RS FF

b)     D FF

c)      JK FF

d)     T FF

 

The above FFs can be designed to trigger for positive edge, negative edge and level sense conditions with Preset, Clear and Enable control conditions.

  1. Adder

a)     Half Adders

b)     Full adders

c)      Carry look  ahead adders

 

  1. Multiplexers, Decoders

a)     4:1 multiplexers         b) 8:1 multiplexers     c) 3  to 8 decoders

  1. Counters

a)     Simple 4 bit binary counter ( 0 to F)

b)     Up/ Down Counter

c)      Mod N Counter

d)     Counters with parallel Load and Clear facility

  1. Shift Registers

a)     Serial In Serial Out                b) Serial In Parallel Out

a)     Parallel In Serial Out             d) Parallel In Parallel Out

  1. Simple Arithmetic Unit implementation

Implementation of

a)     Addition    b)  subtraction   c)  multiplication   d) division

The above operation can be implemented using CASE structure in VHDL

  1. Implementation of Mealy and Moore machine

State machine implementations

  1. RAM implementation

Read and write operation simulation

  1. A simple digital calculator implementation
  2.  Mini Projects

a)              Traffic light controller

b)              Stepper motor controller

c)               Sequence identifier

d)  A/D and D/A

e)   PWM Converter

f)    Microprocessor implementation
  1. References:

1. VHDL                                  - Douglas Perry

2. VHDL Primer                     - J. Bhasker

3. VHDL                                  - Z. Navabi

   NOTE :

·                     One hour instruction class of VHDL syntaxes per lab may be useful.

·                     Public domain tools like MAX PLUS II and AHDL can be used