COMPUTER ARCHITECTURE
CS 242 No. of hrs/week=03+03
No. of credits =04
1. Introduction: Organization and Architecture, Designing for performance, Pentium & Power PC evolution {1.1,2.2,2.3 of tex1} 1hr
2. Computer Components, Computer function, Interconnection structures [3.1-3.3 of Text 1] 3hrs
3. Computer Memory- Characteristics of memory system, Memory hierarchy, Semiconductor Main Memory- RAM & ROM chips, Memory address map, memory connection to CPU [4.1 of text 1 & 12.1 of text 2] 3hrs
Auxiliary Memory – Magnetic Disks, Data organization and formatting physical characteristics, RAID – comparative study of RAID level 0 to RAID level 6 [6.1, 6.2 of tex1] 3hrs
Cache Memory – Cache memory principles, elements of cache design [4.1- 4.3 of Text 1] 2hrs
Virtual Memory: Principle, memory management Hardware[12.6,12.7 of Text 2] 2hrs
4. Instruction set Design : Machine instruction characteristic- types of operands, types of operations, Pentium and Power PC operation types- Pentium operation types : (basic concepts only). Call return instructions
Memory Management, Condion codes, Pentium MMX instructions
Power PC operation types- Branch oriented instructions, Load/ Store instructions, Addressing modes, instruction formats-instruction length, allocation of bits, variable length instructions (exclude PDP & PDP10, PDP 11 & VAX) Pentium and power PC instruction formats[ 10.1-10.5 except 10.3, 11.1-11.4 of Text 1] 5hrs
5. CPU structure and Function: processor organization, register organization, Instruction cycle [12.1-12.3 of Text 1] 3hrs
6. Control Unit Operation: Micro operations, Control of the processor(exclude Intel 8085), hardwired Implementation, micro-programmed control-Basic concepts, micro instructions, micro programmed control unit, wilkes control, microinstruction sequencing – Design considerations, sequencing techniques, Address generation, Microinstruction execution – a taxonomy of micro instructions, microinstruction encoding. [16.1-16.3,17.1-17.3 of Text 1] 5hrs
7. Computer Arithmetic : The ALU, Integer arithmetic, floating point arithmetic [9.1-9.5 of Text 1, all sections must be discussed] 6hrs
8. RISC – CISC characteristics- Reduced Instruction set architecture- CISC characteristics RISC characteristics-comparison, Overlapped register windows, Berkeley RISC [13.4-of Text 1 and 8.8 of Text 2] 2hrs
8. Input – Output: I-O interface, I/O bus & interface modules, I/O verses memory bus, isolated versus memory mapped I/O. Asynchronous Data Transfer- handshaking. Asynchronous serial transfer, Asynchronous communication interface, Modes of transfer-programmed I/O, Interrupt initiated I/O, Direct Memory Access, Priority interrupt-polling, daisy chaining priority, parallel priority interrupt (basic principles only.[11.2-11.6 of text 2 specified sections only]. 6hrs
9. Parallel Processing-Pipelining , arithmetic pipeline, RISC pipeline.
[9.2, 9.3,9.5 of Text 2] 2hrs
11.Multiprocessors, Multiprocessor Organizations: (SISD, SIMD, MISD, MIMD) Interconnection structure, interprocessor arbitration, Interprocessor communication and synchronization, Cache coherence [18.1 of Text 1, 13.2-13.5 of Text 2]. 5hrs
TEXT BOOKS:
1. Computer Organization and Architecture – William Stallings, VI edition, PHI
2. Computer System Architecture- Morris Mano- III Edn, PHI
COMPUTER ARCHITECTURE(PRACTICAL)
The following exercises can be implemented and simulated using VHDL/ Verilog
a) RS FF
b) D FF
c) JK FF
d) TFF
The above FFs can be designed to trigger for positive edge, negative edge and level sense conditions with Preset, Clear and Enable control conditions.
2. Adder
a) Half Adders
b) Full adders
c) Carry look ahead adders
a) 4:1 multiplexers b) 8:1 multiplexers c) 3 to 8 decoders
a) Simple 4 bit binary counter ( 0 to F)
b) Up/ Down Counter
c) Mod N Counter
d) Counters with parallel Load and Clear facility
a) Serial In Serial Out b) Serial In Parallel Out
a) Parallel In Serial Out d) Parallel In Parallel Out
Implementation of
a) Addition b) subtraction c) multiplication d) division
The above operation can be implemented using CASE structure in VHDL
State machine implementations
Read and write operation simulation
a) Traffic light controller
b) Stepper motor controller
c) Sequence identifier
d) A/D and D/A
e) PWM Converter
f) Microprocessor implementation
1. VHDL - Douglas Perry
2. VHDL Primer - J. Bhasker
3. VHDL - Z. Navabi
NOTE :
· One hour instruction class of VHDL syntaxes per lab may be useful.
· Public domain tools like MAX PLUS II and AHDL can be used