Be able to design an n-bit binary ripple counter.
Be able to analyze the operation of non-binary ripple counters.
Be able to interconnect n BCD ripple counters to produce a n digit decade counter.
Be able to design an n-bit synchronous binary counter.
Be able to design an n-bit synchronous counter for any given sequence.
Be able to use parallel load to produce a modulo-N counter.
Be able to define and give an example (in timing diagram form) of word time.
Be able to design a word time generator using a counter, discrete gates and a flip-flop.
Be able to design ring and Johnson counters that generate n-bit timing signals.
Be able to determine the number of address and data lines needed for a 2k word by n bit/word RAM.
Know the sequence of events in a memory write cycle.
Know the sequence of events in a memory read cycle.
Be able to design a 2k word by n bit/word RAM (see Figure 7-27).
Be able to connect RAM chips to produce memory banks that are deeper (more words) and wider (more bits/word) than the individual chips.
Be able to use MAX+plus II or PLDShell to design and implement state machines using PLD's.
Be able to simulate state machine behavior in PLDShell.