| Text: | Mano, M. M. Digital Design, 2nd Ed. Prentice Hall, 1991. |
| Lecture: | 9-10 M, W & F in S-107 |
| Lab: | 8-11 Th in S-314 |
| Course Home Page: | http://www.msoe.edu/~tritt/ee290.html |
| Course Policies: | http://www.msoe.edu/~tritt/policies.html |
| Professor: | Charles S. Tritt, Ph.D. |
| e-mail: | tritt@msoe.edu |
| Office: | S-353A |
| Phone: | 277-7421 (voice), 277-7465 (fax) |
| Office Hours: | M-10, Tu-12 & 3, W-10, Th-12 by appointment |
| Date | Topics, Assignments Due, and Reading |
| 3/10 | Introduction to Course, Number Systems and Binary Arithmetic (1-1 to -6) |
| 3/12 | Binary Codes, etc. (1-7 to -9 and 2-7 to -8) |
| 3/14 | Introduction to Boolean Algebra (2-1 to -2) |
| 3/17 | Boolean Algebra and Functions (2-3 to -4). Happy St. Patrick's Day! |
| 3/19 | Canonical and Standard Forms (2-5 to -6) |
| 3/21 | Karnaugh Maps (3-1 to -4) |
| 3/24 | Products of Sums; etc. (3-5 to -7) |
| 3/26 | Prime Implicants and Introduction to the Tabulation Method (3-9 to 3-12) |
| 3/28 | Good Friday, no school |
| 3/31 | Introduction to Combinational Logic Design; Adders and Substractors (4-1 to -4) |
| 4/2 | Analysis Procedures; etc. (4-5 to -9). Quiz 1 - Covers Chapters 1 through 3-12 (Tabulation Method not stressed) |
| 4/4 | Introduction to MAX+plus II - Combinational (Handout) |
| 4/7 | Introduction to SSI and MSI Devices; Standard Graphic Symbols (12) |
| 4/9 | MSI Devices (5-1 to -4) |
| 4/11 | Decoders, Encoders, Multiplexers and ROM's (5-5 to -7) |
| 4/14 | PAL's, PLA's and PLD's (5-8 to -9 and handouts) |
| 4/16 | Introduction to Synchronous Sequential Logic (6-1 to -3) |
| 4/18 | Analysis of Clocked Circuits and State Reduction and Assignment (6-4 to -5) |
| 4/21 | State Reduction and Assignment and Excitation Tables (6-5 to -6) |
| 4/23 | Design Procedures and Examples (6-7 to -8) |
| 4/25 | Quiz 2 - Covers Chapters 4 and 5 |
| 4/28 | MAX+plus II - Sequential (Handout) |
| 4/30 | Registers (7-1 to -3) and Counters and Timing (7-4 to -6) |
| 5/2 | PLD's, RAM, Memory Decoding and ECC's (handouts and 7-7 to -9) |
| 5/5 | Introduction to ASM's (8-1 to -3) |
| 5/7 | Design of ASM's (8-4 to -6) |
| 5/9 | Quiz 3 - Covers Chapters 6 and 7 |
| 5/12 | Introduction to Asynchronous Sequential Logic (9-1 to -4) |
| 5/14 | Design of Asynchronous Sequential Logic (9-5 to -8) |
| 5/16 | A to D and D to A conversions, Review for final |
| Week | Topics and Type of Report (if any) |
| 1 | Laboratory Equipment and the Analog Behavior of Logic IC's (Informal) |
| 2 | Analysis of SSI Combinational Logic (Informal) |
| 3 | Analysis of MSI Combinational Logic (Informal) |
| 4 | ROM's and PLD's in Combinational Logic (Informal) |
| 5 | Combinational Design Project, Part 1 (Work in groups of 2) |
| 6 | Combinational Design Project, Part 2 (Demonstrations); Combinational Design Report Due Friday, April 25. |
| 7 | Analysis of Sequential Logic (Informal) |
| 8 | Design of Sequential Logic (Informal) |
| 9 | Sequential Design Project, Part 1 (Work in groups of 3) |
| 10 | Sequential Design Project, Part 2 (Demonstrations and Presentations); Sequential Design Report Due Friday, May 16. |
Final: Tuesday 5/20, 8 to 10 am
Homework assignments will be made in class and probably on my web site at about weekly intervals. Homework will be graded on a 0, 50, 100 % scale. Solutions to the homework problems will be placed on reserve at the library after the homework was due. Quizzes will be 20 minutes long. Quizzes are closed book and closed notes, but you may use a one sided 3 by 5 note card on them. The final is open book with a double sided 8 ½ by 11 note card allowed.
You may cooperate and/or work together on all our of class assignments in this course.
Tentative Grade Weights
| Homework | 10% (about 1% each) |
| Labs and Projects | 30% (about 3% each) |
| Quizzes | 30% (10% each) |
| Final | 30% |