Use MAX+plus II or PLDshell Plus to design a 4-bit Gray code to 7-segment Hexadecimal display converter using Altera MAX5000 auto device selection or an Intel 85C220 µPLD.
The Gray code values are as follows:
Value Code Value Code 0 0 0 0 0 8 1 1 0 0 1 0 0 0 1 9 1 1 0 1 2 0 0 1 1 A 1 1 1 1 3 0 0 1 0 B 1 1 1 0 4 0 1 1 0 C 1 0 1 0 5 0 1 1 1 D 1 0 1 1 6 0 1 0 1 E 1 0 0 1 7 0 1 0 0 F 1 0 0 0
The display segments are lettered as follows:
a
--- b | c | d --- e | f | g ---
The characters should be formed as follows:
--- --- --- --- --- ---
| | | | | | | | | |
--- --- --- --- ---
| | | | | | | | | |
--- --- --- --- ---
--- --- --- --- --- ---
| | | | | | | | | | |
--- --- --- --- --- --- ---
| | | | | | | | | | | |
--- --- --- --- --- ---
The digit one is made up of segments d and g.
Turn in paper copies of your source (.TDF) and report (.RPT) files Draw a NAND gate logic diagram for the sum-of-products form of segment e equation.
PLDshell Note: To get the minimizer to produce positive logic sum-of-products equations for this design you must turn Automatic Inversion off under the Compile Options sub-menu and answer no when asked if it is "Okay to use inverted equations?"