MAX+plus II Simulation and Testing

1. These notes describe one way to use MAX+plus II to simulate and test a digital design. Simulation is a complex topic and MAX+plus II provides extensive design simulation and testing support. Only a small fraction of the complete MAX+plus II simulation features and techniques will be covered here. See the MAX+plus II documentation (including online help) for more information.

2. Create or open a project and complete the specification of your design using any valid hierarchy (combination) of .tdf, .wdf and .gdf files and compile it.

3. Select File | New | Text Editor file and enter a vector (.vec) file specifying the simulation. If the vector file has the same name as the project it will automatically be converted into simulator netlist file (.snf) when the simulator is started. A list of statements that can appear in a vector file is provided latter in this document.

4. Switch to the simulator mode by selecting MAX+plus II | Simulator. If your vector file name is different from the project name, select File | Inputs/Outputs, enter the vector file name and click on OK. To simulate a only, leave the Check Outputs box unchecked in the Simulator window. To simulate and test, check the Check Outputs box in the Simulator window.

5. Click on Start. If the simulation is successful, click on Open SCF and view the simulation results. If there are errors in the vector file or the outputs specified in the vector file do not match those generated by the simulation, a message window will open indicating the nature of the errors. Double clicking on the error message will take you to the offending text in the vector file or interval in the simulation output wave file.

Statement Summary

UNIT	Sets the time units as nanoseconds, microseconds, milliseconds or seconds (optional, the default is nanoseconds).
START	Sets the starting time for absolute time patterns (optional, the default is 0).
STOP	Sets the stopping time for absolute time patterns (optional).
INTERVAL	Sets the simulation step interval absolute time patterns (optional, the default is 1 nanosecond).
GROUP CREATE	Creates a group to represent a state numerically (optional).
RADIX	Sets the radix (base) for the group output (optional, default is decimal).
INPUTS	Declares the input nodes (required).
OUTPUTS	Declares the output nodes (optional for simulation only).
BURIED	Declares the buried nodes, if any (optional).
COMB	Specifies that a node declared in a preceding outputs or buried section is driven by combinational logic (optional).
MACHINE	Specifies that a node in a preceding inputs, outputs or buried statement is driven by state machine logic and specifies its secondary inputs (CLOCK, PRESET and RESET). This statement is used only for waveform design entry (optional).
REGISTER	Specifies that a node in a preceding outputs or buried statement is driven by a register and specifies its secondary inputs (CLOCK, PRESET and RESET). This statement is used only for waveform design entry (optional).
PATTERN	Used specify the time patterns (vectors) used in the simulation or test. Just the inputs can be specified to simply simulate a design or the inputs and expected outputs can be specified to simulate and test a design. The two types of time pattern specifications are relative and absolute. Relative time patterns consist of a table of logic values. The number and order of the values should match the nodes specified in the inputs statement. Each set of values corresponds to one time interval. Absolute time patterns allow specification of the exact time at which the logic levels specified are applied to the input nodes (required).