4-Bit Counter Sample

Title     Modified 4-Bit Counter Sample
Author    Chares S. Tritt, Ph.D.
Company   MSOE
Date      02-07-1993

CHIP  my_4_count  INTEL_ARCH ; was 85C224

; pin assignments

PIN	1	CLK	; clock pin
PIN	2	ENA	; counter enable
PIN	15	QA	; LSB
PIN	16	QB
PIN	17	QC
PIN	18	QD	; MSB

; Design as a Moore Machine

STATE
MOORE_MACHINE

; Specify States

S0 = /QD * /QC * /QB * /QA
S1 = /QD * /QC * /QB *  QA
S2 = /QD * /QC *  QB * /QA
S3 = /QD * /QC *  QB *  QA
S4 = /QD *  QC * /QB * /QA
S5 = /QD *  QC * /QB *  QA
S6 = /QD *  QC *  QB * /QA
S7 = /QD *  QC *  QB *  QA
S8 =  QD * /QC * /QB * /QA
S9 =  QD * /QC * /QB *  QA
SA =  QD * /QC *  QB * /QA
SB =  QD * /QC *  QB *  QA
SC =  QD *  QC * /QB * /QA
SD =  QD *  QC * /QB *  QA
SE =  QD *  QC *  QB * /QA
SF =  QD *  QC *  QB *  QA

; State Transitions

S0 := ENABLED -> S1
S1 := ENABLED -> S2
S2 := ENABLED -> S3
S3 := ENABLED -> S4
S4 := ENABLED -> S5
S5 := ENABLED -> S6
S6 := ENABLED -> S7
S7 := ENABLED -> S8
S8 := ENABLED -> S9
S9 := ENABLED -> SA
SA := ENABLED -> SB
SB := ENABLED -> SC
SC := ENABLED -> SD
SD := ENABLED -> SE
SE := ENABLED -> SF
SF := ENABLED -> S0


CONDITIONS

ENABLED = ENA

SIMULATION

; set up vector and trace
; set to known state, preload registers (all low)

VECTOR COUNT := [ QD, QC, QB, QA ]
TRACE_ON  ENA  CLK  QD  QC  QB  QA
SETF  ENA  /CLK
PRLDF  /QA  /QB  /QC  /QD       ; clock set before
                                ; preload command
; count 4 times

    FOR X := 0 TO 3 DO
        BEGIN
            CLOCKF CLK
        END

; disable counting, then try 4 more times

SETF  /ENA
    FOR X:=0 TO 3 DO
        BEGIN
            CLOCKF CLK
        END

; enable counting, then count 10 times

SETF  ENA
    FOR X:=0 TO 9 DO
        BEGIN
            CLOCKF CLK
        END

TRACE_OFF

; end of simulation