Title PLDasm Language Summary
Pattern Label
Revision Number
Author Your Name
Company Your Company
Date 2/17/97
OPTIONS
TURBO = [ON|OFF] ; default is ON
SECURITY = [ON|OFF] ; default is OFF
; design name partname
CHIP template 85Cxxx
;
; Some Available Parts:
; partname speed bins
; 20 pin C/PDIP 85C220 -80(10ns Tpd), -66(12ns Tpd)
; PLCC N85C220 -7, -80(10ns Tpd), -66(12ns Tpd)
; C/PDIP 5C032 -30, -35, -40
;
; 24 pin C/PDIP iPLD22V10 -10, -15
; PLCC iPLD22V10N -10, -15
; C/PDIP iPLD610 -10, -15, -25
; PLCC iPLD610N -10, -15, -25
; C/PDIP 85C224 -80(10ns Tpd), -66(12ns Tpd)
; PLCC N85C224 -7, -80(10ns Tpd), -66(12ns Tpd)
; C/PDIP 85C060 -10, -12, -15
; PLCC N85C060 -10, -12, -15
; C/PDIP 5AC312 -25, -30
; PLCC N5AC312 -25, -30
; C/PDIP 85C22V10 -10, -15
; PLCC N85C22V10 -10, -15
; C/PDIP 5C060 -45, -55
; PLCC N5C060 -45, -55
;
; 28 pin C/PDIP 85C508 -7, -10 ; Decoder/Latch PLD
; PLCC N85C508 -7, -10
;
; 40 pin C/PDIP iPLD910 -12, -15, -20, -25
; PLCC iPLD910N -12, -15, -20, -25
; C/PDIP 85C090 -12, -15, -20, -25
; PLCC N85C090 -12, -15, -20, -25
; C/PDIP 5AC324 -25, -30, -35
; PLCC N5AC324 -25, -30, -35
; C/PDIP 5C090 -50, -60
; PLCC N5C090 -50, -60
;
; 68 pin PLCC N5C180 -70, -75, -90
; PGA A5C180 -70, -75, -90
;
; For futher partname information, see Table 1-1 in the PLDshell Plus Manual.
; Check device data sheets for speed/timing information.
; Extended Temperature/Military versions of most devices are available.
; PINLIST
PIN 1 CLOCK
PIN UPDOWN ; undefined pin assignment
PIN CLEAR
PIN 2 I1 ; Direct Inputs
PIN 3 I2
PIN 4 I3
PIN 5 I4
PIN Q0 ; unassigned state variables a state machine
PIN Q1
PIN Q2
PIN Q3
; -- Output Types --
; Combinatorial Output, I/O Feedback
PIN O1 COMB, PINFBK
; Combinatorial Output, MC Feedback
PIN O2 COMB, CMBFBK
; Combinatorial Output, Reg Feedback (85C22V10 only)
PIN O3 COMB, REGFBK
; Buried Combinatorial Macrocell
PIN O4 CMBFBK, BURIED
; Registered Output, I/O Feedback
PIN O5 REG, PINFBK
; Registered Output, MC Feedback
PIN O6 REG, REGFBK
; Buried Register
PIN O7 REGFBK, BURIED
; -- Input Types --
; Latched Input (5AC312/5AC324)
PIN 5 LIN1 LATCHED
; Registered Input (5AC312/5AC324)
PIN 6 RIN1 REG
; -- String Substitutions throughout file --
STRING QADS ' (ADS * PCLK * /RESET) '
STRING RASON ' ((RAS0 + RAS1) * /IREADY) '
; Design Sections can appear in any order; but the Simulation
; section must appear last
;
; [ STATE ] -- can have multiple machines
; [ EQUATIONS ] -- only one equation section allowed
; [ T_TAB ] -- can have multiple truth tables
; [ SIMULATION ] -- only one simulation section allowed
;
; At least one STATE/EQUATIONS/T_TAB section must appear.
; -- State Machine Format --
STATE [MEALY_MACHINE|MOORE_MACHINE]
; 1 0 specifies output values on hold conditions
OUTPUT_HOLD OUT1 /OUT2
; 0 1 X specifies default output values
DEFAULT_OUTPUT /OUT1 OUT2 %OUT3
; branches for unresolved states
DEFAULT_BRANCH S0 ; go to S0
DEFAULT_BRANCH HOLD_STATE ; stay in current state
DEFAULT_BRANCH NEXT_STATE ; go to next state in assignments list
; State assignments, value of the machine variables for each state.
; Gray code state assignments for a two-bit machine, S0-S3
S0 = /Q1 * /Q0 ; power-up state of Intel PLD Registers
S1 = /Q1 * Q0
S2 = Q1 * Q0
S3 = Q1 * /Q0
; Gray code state assignments for a three-bit machine, S0-S7
S0 = /Q2 * /Q1 * /Q0
S1 = /Q2 * /Q1 * Q0
S2 = /Q2 * Q1 * Q0
S3 = /Q2 * Q1 * /Q0
S4 = Q2 * Q1 * /Q0
S5 = Q2 * Q1 * Q0
S6 = Q2 * /Q1 * Q0
S7 = Q2 * /Q1 * /Q0
; Gray code state assignments for a four-bit machine, S0-SF
S0 = /Q3 * /Q2 * /Q1 * /Q0 ; 0x0
S1 = /Q3 * /Q2 * /Q1 * Q0 ; 0x1
S2 = /Q3 * /Q2 * Q1 * Q0 ; 0x3
S3 = /Q3 * /Q2 * Q1 * /Q0 ; 0x2
S4 = /Q3 * Q2 * Q1 * /Q0 ; 0x6
S5 = /Q3 * Q2 * Q1 * Q0 ; 0x7
S6 = /Q3 * Q2 * /Q1 * Q0 ; 0x5
S7 = /Q3 * Q2 * /Q1 * /Q0 ; 0x4
S8 = Q3 * Q2 * /Q1 * /Q0 ; 0xC
S9 = Q3 * Q2 * /Q1 * Q0 ; 0xD
SA = Q3 * Q2 * Q1 * Q0 ; 0xF
SB = Q3 * Q2 * Q1 * /Q0 ; 0xE
SC = Q3 * /Q2 * Q1 * /Q0 ; 0xA
SD = Q3 * /Q2 * Q1 * Q0 ; 0xB
SE = Q3 * /Q2 * /Q1 * Q0 ; 0x9
SF = Q3 * /Q2 * /Q1 * /Q0 ; 0x8
; state transitions
S0 := VCC -> S1 ; on next clock go to S1
S1 := UP -> S2
+ DOWN -> S4
; output transitions, MOORE
; Moore outputs are default transitions (VCC) only
S1.OUTF := VCC -> LOCAL * /MEMORY * /INTACK ; registered
S2.OUTF = VCC -> ASTRB ; combinatorial
S3.OUTF = VCC -> ASTRB
; output transitions, MEALY
; Mealy's may have conditions on the output transitions
S1.OUTF := DOWN -> LOCAL * /MEMORY * /INTACK ; registered
+ UP -> /LOCAL
S2.OUTF = UP -> ASTRB ; combinatorial
S3.OUTF = VCC -> ASTRB
; input conditions that determine state and output transitions
CONDITIONS
UP = UPDOWN * /CLEAR
DOWN = /UPDOWN * /CLEAR
ACTIVE = /EN + RDY
; Moore machines are level sensitive. The outputs do not change until
; the next clock edge. Mealy machines can generate pulse signals.
; The outputs may change before the next clock edge. See also the
; examples in exmealy1.pds and pulse1.pds.
; -- Boolean Equations section --
EQUATIONS
O1 = ... ; -- Combinatorial Output (COMBINATORIAL)
O1 := ... ; -- Registered (D) Output (REGISTERED)
O1.FB ; -- Feedback path from macrocell (REGFBK, CMBFBK)
O1.IO ; -- Feedback path from I/O pin (PINFBK)
O1.D := ... ; -- Registered (D) Output (REGISTERED)
O1.T := ... ; -- Toggle (T) Output
O1.J := ... ; -- J/K Output (emulated J/K. Synchronized with .CLKF)
O1.K := ...
O1.S := ... ; -- S/R Output (emulated J/K. Synchronized with .CLKF)
O1.R := ...
; -- Control Signals --
O1.CLKF = CLOCK ; Register clock signal
O1.ACLK = CLOCK * ENABLE ; Asynchronous clock signal, from pterm array
; See Chapter 7 in the PLDshell Plus Manual for specific
; device clocking options, and macrocell control signals.
O1.RSTF = CLEAR ; Register Clear signal
O1.SETF = PRESET ; Register Preset signal
O1.TRST = /OE ; OE signal
; -- Logic --
AND1 = IN1 * IN2 ; Logical AND
/NAND1 = IN1 * IN2 ; Logical NAND
OR1 = IN1 + IN2 ; Logical OR
/NOR1 = IN1 + IN2 ; Logical NOR
XOR1 = IN1 :+: IN2 ; Logical XOR
/XOR1 = IN1 :+: IN2 ; Logical XNOR
NOT = /IN1 ; Logical NOT
; -- Truth Table section --
T_TAB ; combinatorial truth table
( I1 I2 I3 I4 >> C1 C2 C3 C4 )
1 0 0 0 : 1 0 0 0
0 1 0 0 : 0 1 0 0
0 0 1 0 : 0 0 1 0
0 0 0 1 : 0 0 0 1
T_TAB ; registered truth table
( I1 I2 I3 I4 :>> R1 R2 R3 R4 )
1 0 0 0 : 1 0 0 0
0 1 0 0 : 0 1 0 0
0 0 1 0 : 0 0 1 0
0 0 0 1 : 0 0 0 1
; -- Simulation section --
SIMULATION
;-- Build vectors of outputs to use as tests for IF's and WHILE's
VECTOR INS := [ IN8,IN7,IN6,IN5,IN4,IN3,IN2,IN1,IN0 ]
VECTOR NUM := [ Q3, Q2, Q1, Q0 ]
VECTOR GLOB := [ ADDR23, ADDR22, ADDR16, ADDR15, ADDR12 ]
;-- Set all inputs to known values
; 0 0 1 0 1
SETF /CLKPIN /ILE I1 /I2 /I3 INS:=0377
;-- Preload registers to known a state (Intel PLD registers power-up to 0)
;-- NOTE: See PLDshell Plus Manual about preload for specific PLD's.
PRLDF /Q0 /Q1 /Q2 /Q3
;-- Clock an input signal 0-->1-->0
CLOCKF CLKPIN
;-- CHECK output values, report any mismatches
; 1 0 0 0 1 1
CHECK O1 /O2 /O3 /O4 O5 O6
;-- FOR loop to count up 6 clocks
FOR j := 0 TO 5 DO
BEGIN
SETF INS := j
CLOCKF CLK
IF ( NUM == 4 ) ; when in state 4
BEGIN
SETF /OE ; disable OE
END
END
;-- loop until OUTA and OUTB are both low
WHILE ( OUTA + OUTB ) DO
BEGIN
CLOCKF ACLK1
END
; end simulation
Send comments and suggestions about this file to:
Dr. Charles S. Tritt
This page last updated 2/17/97