PLDasm Template

Title       PLDasm Template
Pattern     Label
Revision    Number
Author      Your Name
Company     Your Company
Date        2/17/97

OPTIONS

    TURBO    =  ON             ; default is ON
    SECURITY =  OFF            ; default is OFF

CHIP   template        85C224

    ; PINLIST

PIN     1   CLOCK
PIN     2   I1           ; Direct Inputs
PIN     3   I2
PIN         UPDOWN       ; Unassigned pin assignment

PIN         Q0   REG     ; Unassigned outputs - a state machine
PIN         Q1   REG

    ; String substitutions throughout file
    
STRING   QADS    ' (ADS * PCLK * /RESET) '

    ; State machine section
    
STATE  MOORE_MACHINE

    ; Defaults

    OUTPUT_HOLD      OUT1 /OUT2
    DEFAULT_BRANCH S0

    ; State assignments

    S0 = /Q2 * /Q1 * /Q0    ; power-up state of Intel PLD Registers
    S1 = /Q2 * /Q1 *  Q0 
    S2 = /Q2 *  Q1 *  Q0
   
    ; State transitions

    S0 := COND1          -> S1
        + COND2          -> S2

    S1 :=                -> Sx
        +                -> Sx

    ; Output transitions

    S1.OUTF :=  VCC      -> LOCAL * /MEMORY * /INTACK
    S2.OUTF :=  VCC      -> ASTRB                     

    ; Input conditions that determine state and output transitions

CONDITIONS

    ACTIVE = /EN + RDY

    ; Boolean equation section
    
EQUATIONS

    O1.D := I1 * I2 * I3
          + I1 * /I3 * /I4
    O1.CLKF = CLK
    O1.TRST = OEN + /RESET
    O1.RSTF = RESET * ENABLE

    ; Truth table section

T_TAB 
    ( I1 I2 I3 I4  >> C1 C2 C3 C4 )
       1  0  0  0  :   1  0  0  0
       0  1  0  0  :   0  1  0  0
       0  0  1  0  :   0  0  1  0
       0  0  0  1  :   0  0  0  1

    ; Simulation section
    
SIMULATION

    ; Build vectors of outputs to use as tests for IF's and WHILE's

    VECTOR NUM  := [ Q3, Q2, Q1, Q0 ]

    ; Set all inputs to known values
 
    SETF /CLKPIN /ILE  I1 /I2 /I3  INS:=0377

    ; Set all registers to known values (power-up state)
 
    PRLDF /Q0 /Q1 /Q2 /Q3

    ; Clock an input signal  0-->1-->0

    CLOCKF CLKPIN

    ; CHECK output values, report any mismatches

    CHECK O1 /O2 /O3 /O4  O5  O6

    ; FOR loop to count up 6 clocks

    FOR j := 0 TO 5 DO
    BEGIN
        SETF INS := j
        CLOCKF CLK
        IF ( NUM == 4 )     ; when in state 4
        BEGIN
            SETF /OE        ; disable OE
        END
    END

    ; loop until OUTA and OUTB are both low

    WHILE ( OUTA + OUTB ) DO
    BEGIN
        CLOCKF ACLK1
    END

    ; end of template file