Implementing Machines using Flip-flop Excitations Equations
Sequential machines can be implemented directly using flip-flop excitation equations and the PLD's registered output capabilities. Each macrocell is treated as a flip-flop. Inputs to the registers are declared using the following suffixes with the register (macrocell/output) names and the ":=" assignment operator:
| .CLKF | Clock signal (positive edge triggering). |
| .D | Register acts as a type D flip-flop with the specified input. |
| .T | Register acts as a type T flip-flop with the specified input. |
| .J | Signal is treated as the J input of a JK flip-flop. |
| .K | Signal is treated as the K input of a JK flip-flop. |
| .S | Signal is treated as the S input of a SR flip-flop. |
| .R | Signal is treated as the R input of a Sr flip-flop. |
| .RSTF | Clear equation. |
| .SETF | Preset equation. |
Some PLD's allow asynchronous clocks, presets and clears. It is often possible to clock different macrocells on the same chips with different clocks signals.
Implementing Machines using State-Diagram Information
PLDshell Plus provides an alternative to direct implementation of the excitation equations. This alternative involves specifying the machine based on its state diagram. this type of design starts with the STATE command. The format of the STATE sub-section is as follows:
STATE
Machine Type (MOORE_MACHINE or MEALY_MACHINE)
Machine Defaults (OUTPUT_HOLD, DEFAULT_OUTPUT, DEFAULT_BRANCH)
State Assignments
State Transitions
Transition Outputs (may include conditions for Mealy machines)
CONDITIONS (used specify symbolic transition condition names)
EQUATIONS (used to specify clock inputs)
Subsection Formats
State Assignments
State assignments are made by specifying the name of the state, an "=" and a list flip-flop (output, macrocell) names. The states of the flip-flops are specified using prefixes. No prefix means high, while a / means low. The flip-flop names are separated using "*'s". For example:
WAITING = /Q1 * /Q2
State Transitions
State transitions are declared by specifying the present state, a ":=", a condition, a "->" and the next state. Multiple transitions can be specified using a "+", another condition, a "->" and another next state. For example:
WAITING := READY -> GO
+ ERROR -> ALARM
Transition Outputs
Outputs are associated with the present state and, for Mealy machines, the condition. Outputs are declared by specifying the present state with a .OUTF suffix, a ":=", an optional condition followed by "->" and the output names. Conditions are only specified for Mealy machines. Multiple sets of conditions and outputs are separated with "+'s". Prefixes indicate high (none) or low (/) states for the outputs. The output names are separated with "*'s". For example:
GO.OUTF := START * RUN ; Moore machine
GO.OUTF := NO_ERRORS -> START * RUN * /HOLD ; Mealy machine
+ ERRORS -> /START * /RUN * HOLD
CONDITIONS
Conditions specify combinations of inputs that cause transitions. Logical use of conditions make designs easier to understand. Boolean expressions can be used in place of conditions, but should be enclosed in parenthesis. Conditions are defined using a name, a "=" and a Boolean expression. For example:
ERROR = /PAPER + JAMMED + /TONER
EQUATIONS
The equations section is used to specify clock inputs to the flip-flops that define the state of a machine. For example:
Q1.CLKF = CLOCK
See the PLDshell Plus/PLDasm User's Guide V3.0 for more information. User's guides may be checked out form the EECS Technical Support Center.
Send comments and suggestions to: Dr. Charles S. Tritt