PLDshell Plus Simulation Quick Reference

Prepared by Charles S. Tritt, Ph.D.
Version 3.2 (for PLDshell Plus V3.0 and up)
February 15, 1997

The PLDshell simulation feature allows simulation digital designs. The simulation always must be the last section in a source (.PDS) file. The simulation section always starts with the keyword SIMULATION. Simulations provides a means by which the logic levels of various inputs and registers can be set and the resulting outputs observed. Time series simulations are possible for sequential circuits. The use of vectors, bitwise collections of variables, makes simulations more convenient.

Basic Commands

VECTOR Name [msb ... lsb]

Assigns a group of signals to a variable name. The variable will be listed as a numeric value in the simulation output (.HST) file.

SETF Name1 Name2

Sets the designated inputs or states to the specified values. Values are indicated using prefixes. No prefix means high (1), a / means low (0).

SETF VecName := Value

Set the designated vector to the numeric value. The value may be specified in binary, octal, decimal or hexadecimal. The assignment is always made in binary.

PRLDF Name1 Name2

Preloads the designated registers with the indicated levels. Levels are specified using the usual prefix notation (/means low). Clock and control signals should be set before preloading. Not all devices support true preloading.

CLOCKF Name

Cycles the designated signal. Generally used with the system clock. The signal should initialized before cycling.

CHECK Name1 Name2

Checks the specified signals. If the actual state of the signals do not match the expected state, a error message is displayed. Levels are specified using the usual prefixes (/ means low).

Flow Control Commands

BEGIN/END	Defines a sequence of simulation commands to be treated as a block. Used with other flow control commands.
FOR/TO/DO	Loop a specified number of times.
WHILE/DO	Loop while a condition is true (1).
IF/THEN/ELSE	Branch based on a condition.

Flow Control Commands

EXPRESSIONS	Combinations of Boolean expressions and/or conditional relations used with WHILE/DO and IF/THEN/ELSE structures.
CONDITIONALS	Relations used in expressions (=, >, <, >=, /=).
ASSIGNMENTS	Vectors may be assigned any numeric constant (prefix values with #h for hexadecimal, #o for octal or #b for binary) or Boolean expression.

Examples

VECTOR CRL [RDY PWR]	; Combines the RDY and PWR signals into CRL
SETF PWRON /READY	; PWRON set high (1), READY set low (0)
SETF ADDR_BUS := 0xFF	; Sets 8 bit bus to all 1's
PRLDF /Q1 /Q2 /Q3	; Preload Q1, Q2, and Q3 with 0's
CLOCKF CLK		; Cycle the CLK signal
CHECK /DONE		; Display error message if DONE is 1

FOR X := 1 TO 6 DO
	BEGIN
		; Other Statements
	END

WHILE (/ERROR * /DONE) DO
	BEGIN
		; Other Statements
	END

IF (READY) THEN
	BEGIN
		; Other Statements
	END
ELSE
	BEGIN
		; Other Statements
	END

See the PLDshell Plus/PLDasm User's Guide for more information. User's guides may be checked out from the EECS Technical Support Center.