-- From Dr. Ross
-- CE1911
-- 9-May-2016
-- For Lab Weeks 9 & 10
-- A ROM memory, with the memory contents specified by a simple text file.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rom_infer is
   port
   (
      clock: in   std_logic;
		enable: in std_logic;
      read_address:   in   std_logic_vector(11 downto 0);
      q:     out  std_logic_vector (15 downto 0)
   );
end rom_infer;
architecture rtl of rom_infer is
   type mem is array(0 to 4095) of std_logic_vector(15 downto 0);
   signal rom_block: mem;
	attribute ram_init_file: string;
	attribute ram_init_file of rom_block: signal is "twelvebitbcd.mif";
	signal address_integer: integer range 0 to 4095;
begin
	address_integer <= to_integer(unsigned(read_address));
   process (clock)
   begin
      if (clock'event and clock = '1' and enable = '1') then
         q <= rom_block(address_integer);
      end if;
   end process;
end rtl;