Modern microprocessor architectures extend pipelined micro-architecture in a number of ways in order to exploit instruction-level parallelism (ILP) and thread-level parallelism (TLP). Deep pipelines, superscalar pipelines, out-of-order instruction execution, instruction re-ordering and speculative execution are example techniques exploiting ILP. Similarly, multiprocessor techniques such as maintaining a coherent shared memory among multiple cores are examples that exploit thread-level parallelism. These examples challenge the fundamental architectural concept of single-instruction per clock-cycle and result in circuits that improve performance and enrich the user experience. This second course in the MSOE Computer Architecture course series explores these topics through lecture, in-class problems, reading assignments, and homework.
This website serves as the official syllabus. Instructors may provide a supplemental syllabus to students. Use the links at the top of the page to learn about:
Computers serve as the brain in thousands of products that make daily life easier and more interesting. The prerequisite courses have introduced basic digital logic techniques, VHDL description of digital circuits, instruction set architecture, micro-architecture, and performance. This course continues the exploration of computer sytems design by exposing students to the advanced architectural techniques that form the heart of all modern computer systems.
Upon successful completion of this course, students will be able to: