Programmable Logic Devices (PLD's) are the most modern way to implement digital logic designs. We have two software packages for programming PLD's at MSOE. This software can also be used to simplify Boolean logic expressions and simulate digital designs.
| Package | Advantages | Disadvantages |
| PLDshell Plus |
DOS based (runs on most computers). Produces simplified SOP equations for other uses. Can be used to program a wide range of chips on the ChipLab and Chip Master 3000 programmers. Somewhat simpler. |
DOS Based (proprietary interface). Permits only text based design entry. Somewhat dated. |
| MAX+plus II |
Windows Based (common user interface). Permits graphical and timing diagram design entry. More modern. |
Windows Based (requires "high end" computers in S-366 and S-343). Seems to produce only device specific simplifications. Can only be used to program Altera chips on the MPU programmer in S-343. Somewhat more complex. |
PLDshell Plus documentation includes Version 2.3, 3.0 and 3.1 manuals available for checkout at the EECS Technical Support Center, an introductory manual written by Dr. Henry Welch and introductory, sequential machine and simulation quick reference guides written by Dr. Charles S. Tritt.
MAX+plus II documentation includes Version 3.0 manual sets (Getting Started, AHDL and User Guide volumes) available for checkout at the EECS Technical Support Center, Version 5.0 manual sets (Getting Started and AHDL volumes) available for checkout at the Library Circulation Desk under Dr. Ted Robles name for EE-392, etc.
Send comments and suggestions to: Dr. Charles S. Tritt