SE2811
Homework

Homework will be announced in class daily based on the material covered.

Week 1

See Dr. Meier's Homework Set 1

Week 2

  1. Write the complete truth-table for the three-input AND gate.
  2. Write the complete truth-table for the two-input NOR gate
  3. Write the complete truth-table for a two-input NAND gate, where both inputs are "notted". That is: not(not(A) AND not(B)). (See diagram drawn on the board in class)
  4. Draw out a complete transistor-level schematic for a CMOS OR gate.
  5. Exercise 1.78 in the textbook

Week 3

  1. Exercise 1.85 (That is, sketch CMOS NOR, AND, and OR gates.)
  2. Exercise 1.88. (And, for a stretch, 1.87, and 1.90)
  3. Derive the canonical equation for a 3-bit greater-than-3 detector: F(ABC) = 1 if and only if ABC > 3. Draw the gate-level schematic on paper.
  4. Derive the canonical equation for a 4-bit circuit that monitors ABCD and produces a 1 if exactly three bits of ABCD are equal to 1. Draw the gate-level schematic on paper.
  5. Derive the canonical equation for a 4-bit multiple-of-4 detector: F(ABCD) = 1 if and only if 4*j = ABCD for some value of j. Draw the gate-level schematic in Quartus and simulate to verify operation.
  6. Write the long form canonical equation for the function F(ABC) = Sm(4,5,7).
  7. Write the long form canonical equation for the function F(ABC) = Sm(0,1,2,3).

Week 4

  1. Design a minimized SOP (sum-of-products) circuit for a 4-bit greater-than-10 detector. Mathematically, G(ABCD) = 1 if and only if ABCD > 10. Simulate a Quartus schematic blueprint to verify operation. Print your schematic diagram and simulation waveform.
  2. Design a minimized SOP circuit for the function F(ABCD) = AB < CD. Mathematically, F(ABCD) = 1 if and only if two-bit value AB is less than two-bit value CD. Simulate a Quartus schematic blueprint to verify operation. Print your schematic diagram and simulation waveform.
  3. Logic signals P1, P2, and P3 represent power-on signals from the computers of an industrial welding robot in a Harley Davidson motorcycle plant. Signal EMERG represents an emergency stop button placed near the robot so that a human factory worker can shut the system down in there is an emergency. Signal G is the on-off signal for the motors pulling the assembly line chain. This chain moves motorcycle parts past the welding robot. The motors are on when G is on. Derive the K-map minimized logic function for G if G(P1,P2,P3,EMERG) = 1 if and only if at least two of the power signals are on and the emergency stop signal is off. Simulate a Quartus schematic blueprint to verify operation. Print your schematic diagram and simulation waveform.
  4. Reverse-engineer the K-map that was used to derive the minimized logic equation F(ABCD) = D' + BC'. Note that the D' notation means "D bar" or "not D". Calculate the gate reduction ratio.

Week 5

  1. Implement a 5 through 9 detector using a 16-to-1 multiplexer (with inputs ABCD)
  2. Implement a 5 through 9 detector using an 8-to-1 multiplexer (with inputs ABCD)

Week 6

  1. Given a 4-bit bus called g, use a VHDL with-select statement in a dataflow architecture to implement the canonical solution of F(G) = Sm(0,1,2,4,5,6,8,9). Simulate the circuit to verify correct operation. Compare the RTL schematic with your answer to HW 5.1 from last week. Simulat the circuit as a final test that your VHDL code is correct.
  2. Given a 4-bit bus called W with signals W3, W2, W1, and W0, a numeric reverser is a circuit that outputs the input bits in reverse order. In other words, Y3 = W0, Y2 = W1, Y1 = W2, and Y0 = W3. Create the truth table. Implement the numeric reverser as a VHDL with-select architecture. Simulate to verify correct operation. Print VHDL, RTL, and simulation waveforms as part of your submission packet.
  3. The with-select implementation of the numeric reverser is inefficient because it uses multiplexers — and thus logic gates — to reverse the energy bits. An examination of the equations in problem 1 suggests that a simple wiring of input pins to appropriate output pins is all that is needed. VHDL allows direct mapping of inputs to output pins by simply using the assignment arrow ( <= ). Implement the numeric reverser using only input-to-output direct assignment. Simulate to verify correct operation. Print VHDL, RTL, and simulation waveforms as part of your submission packet.

Acknowledgement: Many homework problems originally by Dr. Russ Meier