CE1901
Outcomes

Optional Goodies

Quartus and the DE0 Nano-SoC

Week 1

The first week of CE1901 uses the laboratory period as a fourth lecture period.

In the list below, ✅ indicates an outcome covered on the scheduled day of class. (2_1) indicates an outcome covered on Week 2, Class 1.

In Week 1, many of the outcomes are also discussed on Khan Academy's Binary and hexadecimal number systems. You may find this to be a more detailed supplement than the text, for the material it covers. Outcomes at least partially covered by Khan are indicated by Khan below.

Day 1

  • ✅ Define voltage as electrical potential energy.
  • ✅ Compare and contrast analog and digital voltage signals.
  • ✅ Describe the 0 and 1 concept for digital signals. (Khan?)
  • ✅ Describe positional number systems.
  • ✅ List the powers-of-2 from 1 to 65536. (Khan: to 128 or so)
  • ✅ Compare and contrast decimal digits and binary bits. (Khan)
  • ✅ Convert decimal numbers to binary numbers using the division-by-2 algorithm. (Khan: The other algorithm from the text)
  • (1_2) Write the 3-bit and 4-bit unsigned binary numbers.

Day 2

  • (1_1) Convert binary numbers to decimal numbers using positional multiplication. (Khan)
  • ✅ State the maximum and minimum number on the n-bit unsigned number line.
  • ✅ State the common names given to 4-bit and 8-bit binary numbers.
  • ✅ Describe the octal and hexadecimal number systems. (Khan: Hexadecimal)
  • (1_3) Convert binary numbers to octal numbers.
  • (1_3) Convert binary numbers to hexadecimal numbers. (Khan)
  • (1_3) Convert octal and hexadecimal numbers to binary numbers. (Khan: See my brief answers under the binary to hexadecimal video)

Day 3

  • (Lab 1) Add unsigned binary numbers showing carries between columns. (Khan)
  • (Lab 1) Define unsigned overflow.
  • (Lab 1) Describe how unsigned overflow is identified at the end of a calculation.
  • (Lab 1) Describe the sign-magnitude number line for signed numbers.
  • (Lab 1) State the fundamental flaw with the sign-magnitude representation for negative numbers.

Day 4

  • (Lab 1) Describe the twos-complement number line for signed numbers.
  • (Lab 1) State the maximum and minimum number on the n-bit twos-complement number line.
  • (Lab 1) Convert signed decimal numbers to twos-complement binary numbers.
  • (Lab 1) Convert twos-complement binary numbers to signed decimal numbers.
  • (Lab 1) Add signed binary numbers showing carries between columns.
  • (Lab 1) Define signed overflow.
  • (Lab 1) Describe how signed overflow is identified at the end of a calculation.

Week 2

Day 1

  • ✅ Draw the buffer gate symbol.
  • ✅ Write the truth table for the buffer gate.
  • ✅ Write the Boolean equation for the buffer gate.
  • ✅ Draw the NOT gate.
  • ✅ Write the truth table for the NOT gate.
  • ✅ Write the Boolean equation for the NOT gate.
  • ✅ Draw the logic gate symbols for the 2-input AND, OR, NAND, NOR, XOR, and XNOR gates.
  • ✅ Write the truth tables for the 2-input AND, OR, NAND, NOR, XOR, and XNOR gates.
  • ✅ Write the Boolean equations for the 2-input AND, OR, NAND, NOR, XOR, and XNOR gates.
  • ✅ Extend the AND, OR, XOR, and XNOR gates to n-inputs.

Day 2

  • (2_3) Define the power supply voltages GND and VDD.
  • Contrast the value of VDD common in the 1970s and 1980s technologies with the value of VDD common in today's circuits.
  • Define the driver and receiver in a gate-level interconnection.
  • (2_3) Justify assigning numerical values 0 and 1 to real voltages VOL and VOH.
  • Define noise margin.
  • (2_3) Draw the classic noise margin graph. Identify VOH, VOL, VIL, and VIH on the diagram.
  • Write the noise margin equations NML and NMH.
  • (2_3) Draw the ideal voltage-transfer characteristic (VTC).
  • Explain how the ideal VTC switching threshold of VDD/2 affects noise margins.
  • (2_3) Draw a real VTC curve.
  • Explain how real VTC unity gain points affect the noise margins.
  • (2_3) State the VOH value for 5V TTL.
  • (2_3) State the VOH value for 5V CMOS.
  • Describe the interfacing compatability of the four possibilities of TTL and CMOS interconnection (TTL/TTL, CMOS/CMOS, TTL/CMOS, CMOS/TTL).
  • Define bus. (This term is needed for the Week 3 Lab)

Day 3

  • (2_2) Draw the levels-of-design pyramid showing system level at the top, gate level in the middle, and transistor level at the bottom.
  • (2_3) Describe how encapsulation of components into hierarchical levels makes design diagrams smaller as you move up the levels-of-design pyramid.
  • (2_2) Draw the three-terminal NMOS and PMOS transistor symbols.
  • (2_2) Describe the gate on-off characteristics of NMOS and PMOS transistors.
  • (2_2) Describe the purpose of the pull-up network in a CMOS transistor circuit design.
  • (2_2) Describe the purpose of the pull-down network in a CMOS transistor circuit design.
  • (2_2) State the general rules-of-thumb for CMOS transistor organization in the pull-up and pull-down networks.
  • (2_2) Draw the CMOS schematic for a NOT gate.
  • (2_2) Draw the CMOS schematic for an n-input NAND gate.
  • (2_2) Draw the CMOS schematic for an n-input NOR gate.
  • (2_2) Extend the CMOS NAND and NOR schematics to become AND and OR gates.

Week 3

Day 1

  • ✅ Derive canonical sum-of-product equations from a multi-input truth table.
  • ✅ Define these terms of Boolean algebra: literal, product, minterm.
  • ✅ Identify the literals, products, and minterms in canonical sum-of-product equations.
  • ✅ Draw canonical sum-of-product equations using logic gate symbols.
  • ✅ Calculate the number and type of ideal gates required to implement an equation by inspecting the equation. Use names like AND2 for a 2-input AND gate or OR4 for a 4-input OR gate. Remember that ideal gates can have any number of inputs.
  • (4_3) Identify the circuit elements and circuit nodes in a schematic of a 2-level canonical equation.

Day 2

  • (4_3) Derive more examples of canonical sum-of-products equations from a multi-input truth table.
  • (4_3) Draw more examples of canonical sum-of-products equations using logic gate symbols.
  • (4_3) Write canonical equations in sum-of-minterm (Σ) shorthand notation.
  • (4_3) Derive canonical product-of-sum equations using a multi-input truth table.
  • (5_2) Draw canonical product-of-sum equations using logic gate symbols.
  • (4_3) Write canonical equations in product-of-maxterm (Π) shorthand notation.
  • (5_3) Draw ideal timing diagrams of canonical equations.

Day 3

  • (you already know these) Write the five axioms of Boolean algebra.
  • ✅ Write the Boolean algebra identify theorem (T1).
  • ✅ Write the Boolean algebra null element theorem (T2).
  • (skipped) Write the Boolean algebra idempotency theorem (T3).
  • ✅ Write the Boolean algebra involution "curling or rolling inward" theorem (T4).
  • (skipped) Write the Boolean algebra complements theorem (T5).
  • ✅Recognize that commutativity, associativity, and distributivity from decimal algebra also work when organizing and factoring Boolean algebra.
  • (skipped) Write the Boolean algebra covering theorem (T9).
  • ✅ Write the Boolean algebra combining theorem (T10).
  • (HW 2.3) Write the Boolean algebra De Morgan's Theorem (T12).
  • (HW 2.3) Draw the alternate symbols for NAND and NOR suggested by De Morgan's Theorem. State why these symbols are called duals.
  • (4_2) List the rules of bubble pushing that result from De Morgan's Theorem.
  • ✅ Use the laws of Boolean algebra to reduce canonical equations to minimized equations.

Week 4

Day 1

  • ✅ Use three variable K-maps to design minimized digital logic circuits.
  • ✅ Use four variable K-maps to design minimized digital logic circuits.
  • ✅ Calculate the reduction ratio (minimized gates / canonical gates) for a minimized circuit.
  • ✅ Calculate the input reduction ratio (minimized inputs / canonical inputs) for a minimized circuit.

Day 2

  • (4_3) Use K-maps to implement functions with don't care conditions.
  • (4_3) Compare and contrast the circuits that result from different don't care choices for the same problem.
  • (4_3) Reverse-engineer a K-map and truth table from a given logic circuit.
  • (4_3) Use bubble pushing to convert a K-map minimized sum-of-products logic circuit to a NAND-NAND circuit.

Day 3

  • (4_3) Write the truth table for a 2:1 multiplexer.
  • (4_3) Derive the K-map minimized equation for a 2:1 multiplexer.
  • (4_3) Draw the gate-level circuit for a 2:1 multiplexer.
  • (4_3) Build 4:1, 8:1, and 16:1 multiplexers using 2:1 multiplexers.
  • (5_2) Implement canonical equations using n:1 multiplexers.

Week 5

Day 1

  • ✅ Describe how VHDL separates a circuit description into two parts: entity and architecture.
  • ✅ State the purpose of the VHDL entity declaration.
  • ✅ State the purpose of the VHDL architecture body.
  • ✅ State the purpose of the VHDL library statement.
  • ✅ State the purpose of the VHDL use statement.
  • ✅ Describe the purpose of the standard library called IEEE.
  • ✅ Describe the purpose of the standard IEEE library package STD_LOGIC_1164.all.
  • ✅ Use a K-map to design a minimized logic circuit.
  • ✅ Use VHDL bitwise operators (and, or, not, etc.) to implement the design equation.
  • ✅ Use parenthesis to specify order of operations since VHDL lacks a good default.
  • (See Dr. Meier's notes on PRIME entity) Simulate your VHDL architecture to verify correct operation.
  • (5_2) Use VHDL conditional assignment (when-else) to implement the design equation.
  • (See Dr. Meier's notes on PRIME entity) Simulate your VHDL architecture to verify correct operation.
  • (5_3) Use VHDL selected assignment (with-select) to implement the design equation.
  • (See Dr. Meier's notes on PRIME entity) Simulate your VHDL architecture to verify correct operation.

Day 2

  • ✅ Define bus.
  • ✅ Describe how busses are declared in VHDL.
  • (not repeated) Use a K-map to design a minimized logic circuit.
  • ✅ Use a VHDL input bus for the function variables and VHDL conditional assignment (when-else) to implement the design equation.
  • (See Dr. Meier's notes on PRIME entity) Simulate your VHDL architecture to verify correct operation.
  • (5_3) Use a VHDL input bus for the function variables and VHDL selected assignment (with-select) to implement the design equation.
  • (See Dr. Meier's notes on PRIME entity) Simulate your VHDL architecture to verify correct operation.

Day 3

  • ✅ Compare and contrast structural and behavioral modeling.
  • (6_1) State the purpose of the VHDL signal statement.
  • (6_1) State the purpose of the VHDL component statement.
  • Describe a 2:1 multiplexer in behavioral VHDL.
  • ✅ Implement a 4:1 multiplexer in structural behavioral VHDL.
  • (6_1) Implement a 4:1 multiplexer in structural VHDL.
  • (See Meier's notes) Simulate the 4:1 multiplexer to verify correct operation.
  • Implement a 8:1 multiplexer in structural VHDL.
  • (See Meier's notes) Simulate the 8:1 multiplexer to verify correct operation.

Week 6

Day 1

  • (6_2) Compare and contrast ideal and real gates.
  • (6_2) State why real gates have delay.
  • ✅ List the power-of-10 units used for timing electric circuits. These units represent speeds faster than one second!
  • (6_2) ✅ Define the gate contamination delay.
  • (6_2) Define the gate propagation delay.
  • (6_2) Illustrate contamination and propagation delays on a timing diagram.
  • (6_3) Describe how the critical path affects circuit propagation delay.
  • (6_3) Describe how the shortest path affects circuit contamination delay.
  • (6_3) Calculate the contamination delay for example circuits.
  • (6_3) Calculate the propagation delay for example circuits.

Day 2

  • (6_3) Define glitch.
  • (6_3) Describe why combinational glitches occur.
  • (6_3) Illustrate glitches on timing diagrams.
  • (6_3) State how glitches can be identified in K-maps.
  • (6_3) Eliminate glitches using a consensus term.
  • (6_3) State why glitches cannot be completely removed in most circuits.

Day 3

  • This day is reserved for review or mid-term exams for instructors giving mid-terms.

Week 7

Day 1

  • ✅ Review binary addition and subtraction.
  • ✅ Define bitslice.
  • ✅ Identify the inputs and outputs of a circuit that adds two numbers.
  • ✅ State how the inputs and outputs of the least significant adder column differs from the inputs and outputs of every other column in the adder.
  • ✅ Use a K-map to design the half-adder circuit.
  • ✅ Use a K-map to design the full-adder circuit.
  • ✅ Use the full adder component to design an n-bit ripple-carry adder.
  • ✅ Derive the equation for ripply-carry adder delay.
  • ✅ Extend the ripple-carry adder to a ripple-carry add-subtract component that uses XOR gates and a control signal called SUB to create the twos-complement of B.

Day 2

  • ✅ Describe how carry-lookahead adders improve performance.
  • ✅ Describe the role of the carry and generate signals in the carry-lookahead adder.
  • ✅ Write the generate equation for the i-th bit of an n-bit carry-lookahead adder.
  • ✅ Write the propagate equation for the i-th bit of an n-bit carry-lookahead adder.
  • ✅ Write the carry equation for the i-th bit of an n-bit carry-lookahead adder.
  • ✅ Use recursion to derive the equations for the 4-bit carry-lookahead adder.
  • (7_3) Derive the equation for the carry-lookahead adder delay.

Day 3

  • ✅ Define ALU.
  • (8_1) Define bitslice in the context of ALU design.
  • Describe the role of logic extenders and arithmetic extenders in ALU design.
  • (8_1) Describe role of the control bit and the logical operators in the ALU.
  • (8_1) Implement an ALU bitslice using logic gate symbols.
  • (8_1) Cascade ALU bitslices to create an n-bit ALU.

Week 8

Day 1

  • (8_2) Describe how the n-bit comparator component determines if two numbers are equal.
  • (8_2) Draw the n-bit comparator circuit.
  • (8_2) Compare and contrast shift and rotate.
  • (8_2) Compare and contrast logical shift and arithmetic shift.
  • (8_2) State the mathematical operations completed by shift-left and shift-right.
  • (8_2) Use multiplexers to implement n-bit shifters and rotators.

Day 2

  • ✅ Describe how partial products are created in a binary multiplier.
  • ✅ Draw the 4-bit multiplier circuit using full-adder components and additional AND gates.
  • ✅ State the relationship between m and n if two m-bit numbers are multiplied to produce an n-bit result.
  • (8_3) Describe the multiply-accumulate operation.
  • (8_3) Draw the multiply-accumulate component using a multiplier-component and an adder.
  • (8_3) State the area of algorithms that ofen users multiply-accumulate operations.

Day 3

  • This day is reserved for review.

Week 9

Day 1

  • ✅ Describe an n-bit fixed-point number line.
  • ✅ Write decimal numbers as n-bit fixed-point numbers using a high-word and a low-word.
  • (9_2) Add n-bit fixed point numbers.

Day 2

  • ✅ Explain how floating-point number systems allow representation of very large or very small numbers.
  • ✅ Define mantissa.
  • ✅ Write decimal numbers as IEEE 754 single-precision floating-point binary numbers.
  • (10_1) Write the IEEE 754 floating-point notations for 0, plus and minus infinity, and not-a-number.

Day 3

  • (10_1) Describe how IEEE 754 single-precision and double-precision number lines differ.
  • (10_1) Write decimal numbers as IEEE 754 double-precision floating-point binary numbers.
  • ✅ List the steps for adding IEEE 754 numbers that have the same sign.
  • ✅ Add IEEE 754 single and double-precision floating-point binary numbers

Week 10

Day 1

  • Define programmable logic array (PLA).
  • Describe the general structure of a PLA.
  • Implement canonical equations using a PLA.
  • Reverse-engineer a given PLA to determine the canonical equation and the truth table.

Day 2

  • ✅ Define field programmable gate array (FPGA).
  • ✅ Describe the general structure of an FPGA.
  • ✅ Define logic element (LE).
  • ✅ Define input-output element (IOE).
  • ✅ Draw the basic structure of an FPGA. Do not expand the LE to an internal circuit.
  • (weeks ago) Define look-up table (LUT).
  • (weeks ago) Describe how a multiplexer is used to choose one of the FPGA LUT inputs.

Day 3

  • This day is reserved for a question-answer session before the final exam.

Acknowledgement

The outcomes for this class were taken from Dr. Meier's (the course coordinator's).