CE1911
Outcomes

Optional Goodies

Quartus and the DE0 Nano-SoC

Week 1 Learning Objectives

The first week of CE1911 uses the laboratory period as a fourth lecture period.

In the list below, (2_1) indicates an outcome discussed for the first time on Week 2, Class 1.

Day 1

  • (1_1) Compare and contrast combinational and sequential systems.
  • (1_1) Define the "state" of a memory element.
  • (1_1) Compare and contrast level-sensitive and edge-triggered behavior.
  • (1_1) Describe the role of a clock signal.
  • (1_1) Identify the rising-edge and falling-edge of a clock.
  • (1_2) Define the duty-cycle and period of a periodic clock signal.
  • (1_1) Describe the D flip-flop (DFF) memory behavior.
  • (1_2) Write the truth table of the DFF.
  • (1_1) Draw the logic symbol for the DFF.
  • (1_1) Draw timing diagrams that illustrate DFF behavior.

Day 2

  • (1_2) Draw the logic symbol for the n-bit register.
  • (1_2) Draw the internal circuit of an n-bit register.
  • (1_2) Draw timing diagrams that illustrate register behavior.
  • (1_3) Write the truth table of a DFF with synchronous reset control. (We included the synchronous reset as an input to the circuit -- just like any other synchronous input)
  • (1_3) Draw the logic symbol for a DFF with synchronous reset control. (Quartus doesn't have a DFF with a synchronous reset)
  • (1_4) Write the truth table of a DFF with asynchronous reset control.
  • (1_4) Draw the logic symbol for a DFF with asynchronous reset control.
  • (1_4) Draw timing diagrams that illustrate reset control signals.

Day 3

  • (1_2) Define synchronous sequential circuit.
  • (1_2) Define state.
  • (at some point in early weeks) Define finite state machine.
  • (1_2) Draw the Moore and Mealy FSM models
  • (several times in later weeks)Compare and contrast the Mealy and Moore models.
  • (1_2) Compare and contrast current and next state.
  • (1_2) Define state diagram.
  • (1_3) Draw the state diagram for a Moore FSM to be designed.
  • (1_3) Convert the design state diagram into a design state table.
  • (1_3) Convert the design state table into a truth table using standard binary encoding.
  • (1_3) Derive the next state and output equations from the design truth table.
  • (1_3) Draw the state machine schematic using logic symbols on paper.

Day 4

  • (1_4) Draw the state diagram for a Moore FSM to be designed.
  • (1_4) Convert the design state diagram into a design state table.
  • (1_4) Convert the design state table into a truth table using standard binary encoding.
  • (1_4) Derive the next state and output equations from the design truth table.
  • (1_4) Draw the state machine schematic using logic symbols on paper.
  • (1_4) Draw a timing diagram that illustrates asynchronous reset followed by operational FSM behavior as inputs change.
  • (1_4) Implement the FSM as a Quartus schematic.
  • (1_4) Simulate the FSM in Quartus.

Week 2

Day 1

  • (2_1) Draw the state diagram for a Moore FSM to be designed.
  • (2_2) Convert the design state diagram into a design state table.
  • (2_1) Convert the design state table into a truth table using standard binary encoding.
  • (2_1) Derive the next state and output equations from the design truth table.
  • (2_2) Draw the state machine schematic using logic symbols on paper.
  • (1_3) Draw a timing diagram that illustrates asynchronous reset followed by operational FSM behavior as inputs change. (We did not repeat this -- see previous class)
  • (5_1) State the standard flip-flop and register components from the 7400 logic family.
  • (5_1) Draw the FSM as a 7400 logic family schematic. Note that this schematic must show the chips as rectangles with power, ground, inputs, outputs, and interconnection wires shown.

Day 2

  • (4_1) Define bistable element.
  • (4_1) Draw the basic 1-bit memory as cross-coupled inverters.
  • (4_1) Describe how the 1-bit cross-coupled inverter memory functions.
  • (4_1) Add storage control to the 1-bit memory by replacing the cross-coupled inverters with cross-coupled NOR gates.
  • (4_1) Write the SR-latch truth table.
  • (4_1) Draw the SR-latch logic symbol.
  • (4_1) Describe the SR-latch memory behavior.
  • (4_1) State the SR-latch fundamental control flaw.
  • (4_2) Write the D-latch truth table.
  • (4_2) Draw the D-latch logic symbol.
  • (4_2) Describe the D-latch memory behavior.
  • (4_1) State how the D-latch removes the fundamental control flaw.

Day 3

  • (4_2) Draw the master-slave DFF internal circuit.
  • (4_3) Draw the internal circuit for a DFF with synchronous reset control.
  • (4_2) Draw the internal circuit for a DFF with asynchronous reset control.
  • Write the truth table of a DFF with enable control.
  • Draw the logic symbol for a DFF with enable control.
  • Draw timing diagrams that illustrate enable control signals.
  • (4_3) Draw the internal circuit for a DFF with enable control.
  • Draw the logic symbol for an n-bit register with enable (load) and asynchronous reset (rst) control signals.

Week 3

Day 1

  • (2_2) Describe the VHDL process statement syntax.
  • (2_2) State the role of the VHDL process statement sensitivity list.
  • (2_2) Describe clock edges using VHDL signal attribute syntax (name'event or name'stable).
  • (2_2) Describe clock edges using the VHDL IEEE standard logic library macros rising_edge and falling_edge.
  • (2_3) Write a VHDL description of a 4-bit register.
  • (2_3) Simulate the 4-bit register using Quartus.
  • (2_3) Describe the use of generics in VHDL.
  • (2_3) Write the VHDL description of an n-bit wide register.
  • (2_3) Simulate the n-bit wide register in Quartus.
  • (2_3) Write the VHDL description of an n-bit wide register with asynchronous reset and load set control.
  • (2_3) Simulate the n-bit wide register with asynchronous reset and load set control in Quartus.

Day 2

  • (3_1) Draw the state diagram for a Moore FSM to be designed.
  • (3_1) Convert the design state diagram into a design state table.
  • (3_1) Implement the design FSM using VHDL abstract state types, when-else, and with-select statements.
  • (3_1) Simulate the state machine to verify correct operation.

Day 3

  • (3_2) Draw the state diagram for a Moore FSM to be designed.
  • (3_2) Convert the design state diagram into a design state table.
  • (3_2) Implement the design FSM using VHDL abstract state types and case statements.
  • (3_2) Simulate the state machine to verify correct operation.

Week 4

Day 1

  • (5_2) Describe the one-hot state encoding.
  • (5_2) Draw the state diagram for a Moore FSM to be designed.
  • (5_2) Convert the design state diagram into a design state table.
  • (5_2) Convert the design state table into a truth table using one-hot encoding.
  • (5_2) Derive the next state and output equations from the design truth table.
  • (5_2) Draw the state machine schematic using logic symbols on paper.
  • (5_2) Draw a timing diagram that illustrates asynchronous reset followed by operational FSM behavior as inputs change.
  • (5_2) Draw the FSM as a 7400 logic family schematic.

Day 2

  • (5_3) Draw the state diagram for a Moore FSM to be designed.
  • (5_3) Convert the design state diagram into a design state table.
  • (5_3) Convert the design state table into a truth table using one-hot encoding.
  • (5_3) Derive the next state and output equations from the design truth table.
  • (5_3) Describe the FSM in VHDL using fixed numbers rather than abstract state types.
  • (not repeated) Simulate the FSM in Quartus.
  • (5_3) State why one-hot encoding has become a dominant encoding scheme in FPGA synthesis tools like Quartus.

Day 3

  • Half-Exam 1 will be administered in the first half of class
  • (1_3) Describe Gray Code.
  • (5_3) Draw the state diagram for a Moore FSM to be designed.
  • (5_3) Convert the design state diagram into a design state table.
  • (6_1) Convert the design state table into a truth table using Gray code.
  • (6_1) Derive the next state and output equations from the design truth table.
  • (6_2) Describe the FSM in VHDL using fixed numbers rather than abstract state types.
  • (6_2) Simulate the FSM in Quartus.
  • (6_1) State how Gray Code helps low-power design.

Week 5

Day 1

  • (7_1) Review the Mealy and Mealy machine models.
  • (7_2) Draw the state diagram for a Mealy FSM to be designed.
  • (7_3) Convert the design state diagram into a design state table.
  • (7_3) Convert the design state table into a truth table using standard binary encoding.
  • (7_3) Derive the next state and output equations from the design truth table.
  • (7_3) Draw the state machine schematic using logic symbols on paper.
  • (7_3) Draw a timing diagram that illustrates asynchronous reset followed by operational FSM behavior as inputs change.
  • (not repeated) Draw the FSM as a 7400 logic family schematic. Note that this schematic must show the chips as rectangles with power, ground, inputs, outputs, and interconnection wires shown.

Day 2

  • (8_3) Draw the state diagram for a Mealy FSM to be designed.
  • (8_3) Convert the design state diagram into a design state table.
  • (8_3) Implement the Mealy machine as a one-hot with a full gate-level wiring schematic.
  • (8_3) Register an input to only load the input on an enable signal.
  • (8_3) Review duty cycle, pulse width modulation, etc. for Lab 8
  • (not repeated) Implement the FSM as a VHDL description.
  • (not repeated) Simulate the FSM in Quartus.

Day 3

  • This day is reserved for review or mid-term exams for instructors giving mid-terms.

Week 6

Day 1

  • (6_3) Compare and contrast ideal and real flip-flops.
  • (6_3) State why changing inputs could cause incorrect flip-flop behaviors during clock-edge sampling.
  • (6_3) Define the flip-flop setup time.
  • (6_3) Define the flip-flop hold time.
  • (6_3) Illustrate the flip-flop setup and hold times on a timing diagram.
  • (6_3) Describe the dynamic discipline.
  • (6_3) Examine 7400 family datasheets and identify setup and hold times for various family members.
  • (6_3) Describe the dynamic discipline.
  • (6_3) Define aperture time.
  • (6_3) Define the clock-to-Q contamination delay.
  • (6_3) Define the clock-to-Q propagation delay.
  • (6_3) Illustrate aperture, contamination, and propagation delay on a timing diagram.

Day 2

  • Half-Exam 2 will be administered in the first half of class
  • (7_1) Write the equation for minimum clock period, Tc.
  • (7_1) Write the equation for maximum propagation delay, tpd.
  • (7_1) Define the sequencing overhead.
  • (7_1) Define the setup time constraint.
  • (7_1) Write the equation for minimum propagation delay, tcd.
  • (7_1) Define the hold time constraint.
  • State why hold time constaints are costly.
  • (7_1) Work example problems given flip-flop and logic gate specifications.

Day 3

  • (early in quarter) Define clock skew.
  • (7_2) List factors that contribute to clock skew.
  • (7_2) Describe how clock skew affects the minimum clock period and the maximum propagation delay.
  • Describe how clock skew affects the minimum contamination delay.
  • (7_2) Work example problems given clock skew, flip-flop and logic gate specifications.

Week 7

Day 1

  • (8_2) List the five classic counters.
  • (8_2) Describe the state diagrams of the five classic counters.
  • Draw timing diagrams illustrating the five classic counters with asynchronous reset and load control.
  • (8_2) Compare and contrast saturating and non-saturating counters.
  • Draw saturating and non-saturating counter behaviors on timing diagrams.

Day 2

  • Draw the state diagram for the FSM of a counter to be designed.
  • Convert the design state diagram into a design state table.
  • Derive the output and excitation equations for the design FSM from the design state table.
  • Draw the state machine using logic symbols.
  • Write the VHDL description using abstract state types. Simulate to verify correct operation.
  • Write the VHDL description using fixed numbers instead of abstract types. Simulate to verify correct operation.

Day 3

  • Examine the 74191 datasheet.
  • Modify the 74191 standard counter using control circuitry created with gates so that it counts a modulo-n or BCD sequence.
  • Modify the 74191 standard counter using control circuitry created with gates so that it acts as a saturating counter.
  • Analyze a given 74191 counter circuit to determine the count sequence.
  • Draw timing diagrams of 74191 counter circuit behavior including MAX/MIN and RCO outputs.

Week 8

Day 1

  • (8_2) Describe the basic structure of a memory array.
  • (8_2) Define address.
  • (8_2) Define data.
  • (8_2) Define address bus.
  • (8_2) Define data bus.
  • (8_2) Define word.
  • (8_2) List the standard JEDEC memory size prefixes from kilo through Peta.
  • (8_2) Match the standard JEDEC memory size prefixes with the corresponding power-of-2 memory array depth depth.
  • (8_2) Draw a simple block diagram of the memory bit cell.
  • (8_2) Draw a simple block diagram of an MxN memory array.
  • (8_2) Describe the role of the decoder in the MxN memory array.
  • (8_2) Describe how data is read and written from an MxN memory array.
  • Compare and contrast single and multi-ported memories.

Day 2

  • (8_2) Compare and contrast volatile and non-volatile memories.
  • (9_3) Compare and contrast RAM and ROM memories.
  • (9_3) Compare and contrast static and dynamic RAM. (and flip-flops)
  • (9_3) List the five principle types of ROM.
  • (9_3) Compare and contrast the five principle types of ROM.
  • Use ROM memories to implement look up tables for the next state and output equations for a FSM.
  • (8_3) Use ROM memories to implement binary to decimal conversion

Day 3

  • (8_3) Read timing specifications
  • (8_3) Determine clock period from clock frequency.
  • (8_3) Remember SI multipliers from femto through Peta.
  • (8_3) Invert SI multipliers
  • (8_3) Design a state machine using helper counters.
  • (10_1) Define register file.
  • Design and simulate a VHDL register file description.
  • Design and simulate a VHDL SRAM description.
  • (example provided with Week 9 & 10 lab) Design and simulate a VHDL ROM description.

Week 9

Day 1

  • (10_1) Draw the basic data path model showing the shared data path, data path multiplexer, ALU, register file, and controller.
  • Define register transfer language (RTL).
  • (10_1) Derive RTL microcode to complete some calculation on the basic data path model.

Day 2

  • (10_2) Draw the basic data path model showing the shared data path, data path multiplexer, ALU, register file, and controller.
  • (10_2) Derive RTL microcode to complete some calculation on the basic data path model.

Day 3

  • (not repeated) Draw the basic data path model showing the shared data path, data path multiplexer, ALU, register file, and controller.
  • (not repeated) Derive RTL microcode to complete some calculation on the basic data path model.

Week 10

Day 1

  • Describe how the controllers of special-purpose data paths are modified to calculate multiple functions.
  • (10_1 very high level) Describe the role of the instruction decoder.
  • Draw the basic data path model showing the shared data path, data path multiplexer, ALU, register file, and multi-instruction controller.
  • Derive RTL microcode to complete some set of calculations on the special-purpose data path.
  • Describe the and simulate the controller in VHDL.

Day 2

  • Draw the basic data path model showing the shared data path, data path multiplexer, ALU, register file, and multi-instruction controller.
  • Derive RTL microcode to complete some set of calculations on the special-purpose data path.
  • Describe the and simulate the controller in VHDL.

Day 3

  • This day is reserved for a question-answer session before the final exam.

Acknowledgement

The outcomes for this class were taken from Dr. Meier's (the course coordinator's).