1/19 |
N/A |
Introduction |
|
1/21 |
N/A |
Review and Foundations - Logic and Arithmetic Review |
|
1/26 |
N/A |
Review and Foundations - Technology Review |
|
1/28 |
N/A |
Review and Foundations - Architecture and Operation |
|
2/2 |
Ch. 1 |
Review and Foundations - Computer System Performance |
|
2/4 |
Ch. 2 |
Review and Foundations - Instruction Set Architecture |
|
2/9 |
|
Test 1 review |
|
2/11 |
Ch. 3 |
The Processor - ALU Design |
|
2/16 |
|
Test 1 |
|
2/18 |
Ch. 4 |
The Processor - Data Path |
|
2/23 |
Ch. 4 |
The Processor - Pipelining |
|
2/25 |
Ch. 4 |
The Processor - Pipelining with Hazards |
|
3/1 |
Ch. 4 |
The Processor - Pipelining and Parallel Processing |
|
3/3 |
Ch. 4 |
The Processor - TBD |
|
3/8 |
|
Test 2 review |
|
3/10 |
|
Test 2 |
|
3/15 |
|
No Class |
|
3/17 |
|
No Class |
|
3/22 |
Ch. 5.1, 5.2 |
Memory - Memory Overview |
|
3/24 |
Ch. 5.3 |
Memory - Cache Basics |
|
3/29 |
Ch. 5.4 |
Memory - Cache Performance |
|
3/31 |
Ch. 5.6, 5.7 |
Memory - Virtual Memory |
|
4/5 |
Ch. 5.5, 5.9, 5.10 |
Memory - Cache Control |
|
4/7 |
Ch. 5.8, 5.13 |
Memory - Cache Summary |
|
4/12 |
|
Parallel Processing - Challenges |
|
4/14 |
Ch. 6.1 - 6.3 |
Test 3 review |
|
4/19 |
|
No Class - URAD |
|
4/21 |
|
Test 3 |
|
4/26 |
Ch. 6.4,5,7,8,9 |
Parallel Processing - Architectures |
|
4/28 |
Appendix C |
Parallel Processing - GPU |
|
5/3 |
Ch. 6.10,11 |
Parallel Processing - Performance Measurement, test 4 review |
|
5/5 |
|
Test 4 |
|